DRAM Vulnerable Word-Line Protection with Randomized Adjacent Refresh

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Solution Overview

Problem

Dynamic random access memory (DRAM) systems are vulnerable to the row hammer effect, where malicious operators can change the content of nearby memory rows by rapidly activating the same memory rows, leading to data loss due to charge leakage in adjacent memory cells.

Innovation Solution

A protection circuit is implemented in the DRAM that includes a random number generator and counter to randomly select and protect vulnerable word lines by generating a random number based on the last refreshed and accessed word line addresses, with a number trimmer ensuring the number of activations does not exceed the maximum between refresh cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If DRAM systems use periodic refresh cycles to maintain data, then data retention is improved, but vulnerability to row hammer attacks increases due to repeated activation of same word lines

Engineering Contradiction:
Improvedata retentionVSAvoidrow hammer vulnerability
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by proactively identifying and protecting vulnerable word lines before row hammer attacks can occur. The system monitors access patterns and pre-markes word lines that are frequently accessed or adjacent to frequently accessed word lines, refreshing them in advance during refresh cycles to prevent charge leakage and data corruption before they happen.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by continuously monitoring word line access patterns and using this information to dynamically adjust refresh strategies. The system tracks which word lines are accessed frequently and uses this feedback to identify vulnerable adjacent word lines, then applies targeted refresh operations to protect against row hammer effects based on real-time usage patterns.

Inventive Principle:
Principle #23Feedback

2Speed

If the same memory rows are rapidly activated multiple times, then access speed is improved, but charge leakage in adjacent memory cells increases causing data loss

Engineering Contradiction:
Improvememory access speedVSAvoidcharge leakage
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent applies local quality by applying different refresh strategies to different word lines based on their specific vulnerability characteristics. Instead of uniformly refreshing all word lines, the system identifies locally vulnerable word lines (those adjacent to frequently accessed word lines) and applies targeted refresh operations only to these specific regions, optimizing protection while minimizing overall refresh overhead.

Inventive Principle:
Principle #3Local quality

3Reliability

If protection circuitry is added to prevent row hammer effects, then security is improved, but device complexity increases

Engineering Contradiction:
Improvesecurity against row hammerVSAvoidprotection circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a protection mechanism that serves multiple functions within the memory controller. The same circuitry that manages normal refresh operations is also used to identify and protect vulnerable word lines, and the access pattern monitoring serves both performance optimization and security purposes, reducing the need for separate dedicated protection circuits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12431185B2Memory devices including mechanism of protecting a vulnerable word line based on the previous refreshed word lines and relevant methods
Publication Date: 2025.09.30 NAN YA TECH
  • US12431185B2 patent drawing
  • US12431185B2 patent drawing
  • US12431185B2 patent drawing

AI summary

A memory device and a method for protecting the same are provided. The memory device includes: a random number generator, a counter, and a controller. The random number generator includes a first logic gate and a second logic gate configured to generate a first output and a second output, respectively, according to the address of the first word line and the address of the first accessed word line. The random number generator further includes a switch configured to select one of the first output and the second output to be a first number. The counter is configured to receive the first number and count down from the first number. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh adjacent word lines of the second accessed word line during a second refresh cycle.