DRAM Rank Interleaving for Parallel Data and Metadata Access

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Solution Overview

Problem

Existing memory systems face inefficiencies in utilizing memory bandwidth due to metadata operations, which often result in reduced data access speeds and increased overhead, particularly when metadata and data are stored in the same memory array, leading to suboptimal utilization of available bandwidth.

Innovation Solution

Implementing interleaved data access operations across multiple ranks of a memory system, where metadata and data operations are performed in parallel, reducing the overhead associated with metadata access and enhancing the efficiency of memory device operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If metadata and data are stored in the same memory array, then memory bandwidth utilization is reduced, but storage efficiency is improved

Engineering Contradiction:

Improvememory bandwidth utilizationVSAvoiddata access speed

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The memory system is divided into multiple ranks, with each rank independently accessible. Metadata operations are directed to specific ranks while data operations access other ranks, segmenting the memory access paths to prevent interference between metadata and data transactions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of access by utilizing multiple memory ranks simultaneously. Instead of sequential access within a single rank, the system performs parallel operations across different ranks, effectively adding a spatial dimension to memory access operations.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If metadata operations are performed sequentially with data operations, then overhead is reduced, but access efficiency deteriorates

Engineering Contradiction:

Improvecache access efficiencyVSAvoidoperation scheduling complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The memory controller continuously utilizes available memory bandwidth by initiating metadata operations on one rank while data operations are in progress on another rank. This continuous utilization eliminates idle bandwidth periods and maintains high productivity throughout the operation sequence.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The system performs preliminary actions by pre-fetching or pre-processing metadata in parallel with data operations. By initiating metadata operations before they are strictly needed for subsequent processing, the system overlaps execution phases and reduces total completion time.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12487925B2Rank interleaving for system meta mode operations in a dynamic random access memory (DRAM) memory device

Publication Date: 2025.12.02 QUALCOMM INC

AI summary

This disclosure provides systems, methods, and devices for memory systems that support processing data and metadata within a memory of a memory device. In a first aspect, a method of controlling a memory device includes executing a first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion; and executing a second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank. Other aspects and features are also claimed and described.