DRAM Chip Rank Identification Circuit Using TSV Voltage Division
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Solution Overview
Problem
Current dynamic random-access memory integrated circuits (DRAM ICs) have limited area and require stacking via through silicon vias (TSVs) for increased capacity, necessitating effective chip rank identification to correctly access stacked DRAM ranks.
Innovation Solution
A chip rank identification circuit utilizing a detection circuit with switching and control circuits, resistor networks, and identification circuits to determine chip rank based on voltage readings from TSV connections, optimizing TSV usage by requiring only two connections per chip pair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple TSVs are used for chip stacking, then chip capacity and stacking capability are improved, but TSV area usage and manufacturing complexity increase
Solution Approach 1:
The patent makes TSVs serve multiple functions: they simultaneously provide electrical connection between stacked chips and convey rank identification information. By embedding resistor circuits within TSV structures and using voltage division techniques, the same physical TSVs that connect chips also enable rank detection, eliminating the need for separate identification TSVs and reducing overall TSV area requirements.
Solution Approach 2:
The patent changes the electrical parameters of TSVs by incorporating resistor circuits with different resistance values into different TSVs. This allows rank identification through voltage division measurements without requiring additional TSVs. The resistance values serve as encoding parameters that identify chip rank positions in the stack.
2Adaptability or versatility
If rank identification circuit is added to each chip, then chip rank detection capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the rank identification function from complex active circuits and implements it using passive resistor elements embedded in TSVs. The actual rank detection logic is performed by a simple control circuit that measures voltage divisions, rather than requiring complex identification circuits in each chip. This separates the identification encoding (in TSVs) from the detection logic (in control circuit).
Solution Approach 2:
The patent introduces a control circuit as an intermediary that performs the actual rank detection by measuring voltages at TSV contact points. This control circuit simplifies the overall system by centralizing the detection function rather than requiring complex circuits in each stacked chip. The control circuit uses simple voltage division measurements to determine chip ranks.
3Ease of manufacture
If conventional TSV stacking is used without rank identification, then manufacturing process is simpler, but correct access to stacked DRAM ranks cannot be achieved
Solution Approach 1:
The patent incorporates rank identification resistors into TSVs during the manufacturing process itself, before chips are stacked. The resistor circuits are embedded in the TSV structures during fabrication, so that when chips are stacked, the rank identification information is already present and automatically detected by the control circuit through voltage measurements. This eliminates the need for post-assembly rank configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively identifies chip ranks while minimizing TSV area usage, enabling efficient access to stacked DRAM ranks.
Implementation Method 1
the identification circuit is coupled to the resistor circuit and determines the rank of the chip based on a reference voltage provided by the resistor circuit
Implementation Method 2
The first control circuit is coupled to the first switching circuit and the second contact and determines whether the chip is coupled to a post-stage chip based on a voltage on the second contact
Data Source
AI summary
A chip rank identification circuit is provided. A first control circuit couples a resistor circuit to a first operating voltage or a first contact based on whether a chip is connected to a ost-stage chip. A second control circuit couples the resistor circuit to a second operating voltage or a third contact based on whether the chip is connected to a pre-stage chip. An identification circuit determines a rank of the chip based on a reference voltage provided by the resistor circuit.