DRAM Read Bus Inversion Circuit for Lower Power and Signal Integrity
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Solution Overview
Problem
In the field of semiconductor memory technologies, particularly in DRAM, there is a need to enhance power-saving while ensuring signal integrity and data reliability, which existing technologies have not adequately addressed.
Innovation Solution
A read operation circuit is introduced that includes a data determination module, a data receiving module, a parallel-to-serial conversion circuit, a data buffer module, and a precharge module, which determines whether to invert read data based on the number of bits of low data and transmits it through a global bus with an inversion flag signal, optimizing data transmission and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data inversion is performed on the global bus to balance signal levels, then signal integrity is improved, but power consumption increases due to additional inversion operations
Solution Approach 1:
The patent applies data bus inversion (DBI) technique where the entire data bus is inverted before transmission when the number of logical one bits is less than logical zero bits, and vice versa. This inversion principle balances the signal levels on the global bus, ensuring signal integrity while the patent simultaneously optimizes power consumption by selectively applying inversion only when necessary and using the inverted state as the transmitted data
Solution Approach 2:
The patent changes the parameter of data representation by inverting the logical states (0 becomes 1, 1 becomes 0) based on the content analysis of the data to be transmitted. This parameter change allows the system to maintain signal integrity through balanced voltage levels while reducing the need for additional inversion operations during transmission, thereby optimizing power consumption
2Use of energy by moving object
If the number of inversions on the global bus is reduced to save power, then power consumption decreases, but signal integrity may be compromised
Solution Approach 1:
The patent performs preliminary analysis of the data content before transmission to determine the optimal inversion strategy. By counting the number of logical one bits and zero bits in advance, the system decides whether to invert the data bus before transmission, ensuring that signal integrity is maintained from the outset while minimizing unnecessary inversion operations that would increase power consumption
Solution Approach 2:
The patent incorporates feedback mechanisms where the system monitors the data content and adjusts the inversion strategy accordingly. Based on the feedback from bit counting and data pattern analysis, the system dynamically decides whether to apply inversion, ensuring signal integrity is maintained while optimizing power consumption by avoiding redundant inversion operations
Data Source
AI summary
Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of low data in the read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of the DQ port; and a precharge module configured to set an initial state of the global bus to High.