DRAM Read Register Timing Alignment Across Memory Banks
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Solution Overview
Problem
The timing mismatch between asynchronous sampling signals and global data in dynamic random access memory (DRAM) due to process variations and temperature fluctuations leads to sampling errors, affecting the accuracy of data transfer.
Innovation Solution
Implementing a control signal synthesis circuit that equalizes the path lengths for control signals from multiple memory banks to a read register, ensuring synchronized data sampling by generating an overall control signal that aligns with the arrival times of individual bank signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If asynchronous sampling signals are used in DRAM, then data transfer speed is improved, but timing mismatch occurs due to process variations and temperature fluctuations leading to sampling errors
Solution Approach 1:
A delay circuit is introduced as an intermediary component between the sampling signal generation and the actual sampling operation. This delay circuit adjusts the timing of the sampling signal to compensate for path length differences, ensuring that the sampling signal arrives at the optimal moment despite variations in process and temperature. The delay circuit acts as a mediator that reconciles the speed advantage of asynchronous sampling with the timing precision requirement.
Solution Approach 2:
The system performs preliminary adjustment of the sampling signal timing through the delay circuit before the actual sampling operation occurs. By pre-compensating for expected timing mismatches based on path length calculations, the system ensures that when the sampling signal reaches the data path, it is already properly synchronized, preventing sampling errors before they can occur.
2Device complexity
If path lengths for control signals from multiple memory banks are not equalized, then device complexity is reduced, but timing mismatch occurs affecting data transfer reliability
Solution Approach 1:
Instead of requiring all signal paths to be uniformly equalized throughout the entire system, the invention applies local quality adjustment by introducing delay circuits only at specific locations where timing mismatches occur. Each delay circuit is tailored to compensate for the specific path length difference of its associated memory bank, providing precise timing correction without unnecessarily complicating the overall system architecture.
Data Source
AI summary
Memories, operation methods and memory systems are provided. An example memory includes M memory banks and a peripheral circuit including a control signal synthesis circuit and a first read register. The control signal synthesis circuit includes input terminals and a first output terminal. Each input terminal is connected with one corresponding memory bank and the first output terminal is connected with the first read register. The control signal synthesis circuit is configured to receive control signals through input terminals and output an overall control signal through the first output terminal. A path from each input terminal to the first output terminal in the control signal synthesis circuit has a same length. The first read register is configured to receive the overall control signal and data read from at least one of the M memory banks and output the read data based on the overall control signal.