DRAM Read-Write Data Path Split for Low-Latency Memory Access
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Solution Overview
Problem
Existing DRAM architectures are limited by external bus turnaround times, leading to increased latency and reduced bandwidth in memory access operations.
Innovation Solution
Implementing dedicated unidirectional read and write data paths within the DRAM device, allowing for concurrent memory access operations independent of external bus turnaround times, and incorporating selector circuitry to selectively couple these paths to the memory core on a bank or bank group basis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If shared bidirectional data paths are used in existing DRAM architectures, then device complexity is reduced, but latency increases and bandwidth is limited by external bus turnaround times
Solution Approach 1:
The patent divides the data path into separate unidirectional read and write paths, segmenting the shared bus into dedicated channels. This segmentation allows concurrent operations without turnaround time delays, directly reducing latency while the selector circuitry manages the increased complexity through controlled switching between paths.
Solution Approach 2:
The patent introduces selector circuitry as an intermediary component that manages the switching between read and write paths. This mediator enables the system to achieve low latency by directing data flow through appropriate paths while containing the complexity through centralized control logic.
2Productivity
If dedicated unidirectional read and write data paths are implemented, then bandwidth is improved by a factor of two and latency is reduced, but device complexity increases due to additional selector circuitry
Solution Approach 1:
The data transmission path is segmented into separate unidirectional read and write channels, allowing simultaneous operations without mutual interference. This segmentation doubles the effective bandwidth by eliminating bus turnaround times and the selector circuitry manages complexity through deterministic switching control.
3Speed
If dedicated read and write data paths are used, then read-to-write and write-to-read turnarounds are enabled at faster speeds, but the number of required data paths and selector circuitry increases
Solution Approach 1:
The patent implements dynamic switching through selector circuitry that adapts the data path configuration based on the current operation type (read or write). This dynamic reconfiguration enables fast turnarounds by pre-establishing the appropriate path before each operation, while the controlled nature of the switching keeps complexity manageable.
Data Source
AI summary
Memory devices, modules, controllers, systems and associated methods are disclosed. In one embodiment, a dynamic random access memory (DRAM) device is disclosed. The DRAM device includes memory core circuitry including an array of DRAM storage cells organized into bank groups. Each bank group includes multiple banks, where each of the multiple banks includes addressable columns of DRAM storage cells. The DRAM device includes signal interface circuitry having dedicated write data path circuitry and dedicated read data path circuitry. Selector circuitry, for a first memory transaction, selectively couples at least one of the addressable columns of DRAM storage cells to the dedicated read data path circuitry or the dedicated write data path circuitry.