DRAM Receiver Equalization Using Internal Clock Phase Compensation
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Solution Overview
Problem
Conventional receiving apparatuses in DRAM interface systems face challenges such as increased latency, chip area, and power consumption due to the need for frequent measurement of channel characteristics, which is not feasible in these systems.
Innovation Solution
A receiving apparatus with a clock generating unit and an equalization receiving unit that generates internal clock signals, determines an offset value and equalization coefficient, and adjusts the received data signal to perform digital compensation with reduced power consumption and chip area, specifically designed for DRAM interface systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If adaptive equalizer and CDR are employed to reduce noise and synchronize clock signals, then data transmission reliability is improved, but power consumption and chip area increase
Solution Approach 1:
The patent extracts and removes the adaptive equalizer and CDR circuits from the receiving apparatus, eliminating the source of high power consumption while maintaining data transmission reliability through alternative means
Solution Approach 2:
The patent discards the conventional adaptive equalizer and CDR approach, recovering functionality through simplified timing recovery and equalization methods that consume less power
2Reliability
If adaptive equalizer and CDR are employed to reduce noise and synchronize clock signals, then data transmission reliability is improved, but chip area increases
Solution Approach 1:
The patent extracts and removes the adaptive equalizer and CDR circuits from the receiving apparatus, eliminating the source of large chip area occupation while maintaining data transmission reliability through alternative means
Solution Approach 2:
The patent discards the conventional adaptive equalizer and CDR approach, recovering functionality through simplified timing recovery and equalization methods that occupy less chip area
3Reliability
If adaptive equalizer and CDR are employed to reduce noise and synchronize clock signals, then data transmission reliability is improved, but latency increases
Solution Approach 1:
The patent extracts and removes the adaptive equalizer and CDR circuits from the receiving apparatus, eliminating the source of increased latency while maintaining data transmission reliability through alternative means
Solution Approach 2:
The patent discards the conventional adaptive equalizer and CDR approach, recovering functionality through simplified timing recovery and equalization methods that introduce less latency
Data Source
AI summary
Example embodiments relate to a receiving apparatus and method thereof. In an example, the receiving apparatus may include a clock generating unit generating a plurality of internal clock signals based on a received external clock signal and an equalization receiving unit receiving the plurality of internal clock signals and an input signal. The equalization receiving unit may determine an offset value and an equalization coefficient in an initial setting mode and may adjust the received data signal based on the determined offset value and equalization coefficient.