DRAM Refresh Scheduling for Predictable Memory Access
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Solution Overview
Problem
The non-deterministic nature of DRAM accesses due to refresh and maintenance cycles introduces unpredictable latency and bandwidth issues in real-time systems, hindering efficient and predictable computing, especially in systems requiring deterministic performance.
Innovation Solution
A mechanism is introduced to synchronize DRAM access requests with DRAM controller refresh and maintenance schedules to avoid conflicts, ensuring that DRAM access requests do not collide with refresh or maintenance cycles, thereby maintaining predictable latency and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM is used for primary memory storage, then large capacity and cost-effectiveness are achieved, but access latency becomes unpredictable due to refresh and maintenance cycles
Solution Approach 1:
The patent segments the memory system into two parts: SRAM cache for frequently accessed data and DRAM for bulk storage. This segmentation allows the system to maintain large capacity while ensuring predictable access latency for critical operations by serving them from the deterministic SRAM cache.
Solution Approach 2:
The patent implements preliminary action by pre-loading data from DRAM into SRAM cache before it is needed for processing. This anticipatory data movement ensures that when data is required, it is already available in the fast, predictable SRAM, eliminating latency variability caused by DRAM refresh cycles.
2Speed
If SRAM cache is added to reduce DRAM access latency, then access speed improves, but system complexity increases
Solution Approach 1:
The patent makes the SRAM cache universally applicable to all DRAM access operations. The cache subsystem serves multiple functions: storing frequently accessed data, buffering data during DRAM refresh cycles, and providing predictable access paths. This multi-functionality justifies the added complexity by delivering comprehensive performance benefits across all memory operations.
3Reliability
If DRAM refresh cycles are performed periodically, then data integrity is maintained, but access bandwidth becomes unpredictable
Solution Approach 1:
The patent introduces the SRAM cache as an intermediary between the processor and DRAM. During DRAM refresh cycles, the cache maintains data locally, allowing the processor to continue accessing data through the cache without being blocked by DRAM refresh operations. This intermediary buffer preserves data integrity while maintaining consistent bandwidth.
4Reliability
If maintenance updates are performed on DRAM controller, then signaling reliability improves, but access latency increases unpredictably
Solution Approach 1:
The patent performs maintenance updates on the DRAM controller during periods when data is being transferred from DRAM to SRAM cache or when the cache already contains the required data. This timing strategy ensures that maintenance operations do not block critical data paths, maintaining signaling reliability while minimizing impact on access latency.
Data Source
AI summary
When reading and writing DRAM (dynamic random-access memory), the latency and bandwidth is often unpredictable with large variations. One reason is because all the DRAM memory banks require periodic refreshes and maintenance cycles that interrupt these accesses. DRAM refresh and maintenance cycles are synchronized with the read/write accesses in a mutually exclusive manner, hence, preventing the accesses from being interfered with by a refresh or maintenance cycle resulting in predictable latency and bandwidth performance during read/write operations.