Per-Bank DRAM Refresh Counters for Asynchronous Refresh Scheduling
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Solution Overview
Problem
Current DRAM devices face inefficiencies in refresh operations due to simultaneous bank refreshes, leading to increased power consumption and reduced flexibility in scheduling, especially in low-power applications, and existing per-bank refresh schemes require significant overhead in the memory controller to manage refresh commands.
Innovation Solution
Implementing multiple refresh address counters, one for each bank, allows independent refresh operations, enabling asynchronous refresh scheduling and reducing power consumption by allowing banks to be refreshed independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all banks are refreshed simultaneously with a single refresh command, then refresh operation is simplified and all banks are refreshed efficiently, but power consumption increases and flexibility in scheduling is reduced
Solution Approach 1:
The invention divides the single refresh counter into multiple per-bank refresh counters (one counter per bank). This segmentation allows each bank to be refreshed independently with its own counter, enabling the memory controller to select which banks to refresh based on power management requirements and activity patterns, thus reducing overall power consumption while maintaining refresh efficiency.
Solution Approach 2:
The invention implements dynamic refresh scheduling where the memory controller can adaptively select which banks to refresh based on current system conditions. The per-bank counters enable the controller to dynamically adjust refresh operations, refreshing only active banks or banks that are not currently being accessed, thereby optimizing power consumption in real-time.
2Loss of time
If all banks are refreshed simultaneously, then refresh overhead is reduced, but the memory controller must wait for all banks to complete refresh before handling read/write requests
Solution Approach 1:
By segmenting the refresh operation into per-bank independent operations with separate counters, the system can refresh individual banks without halting all memory operations. The memory controller can issue refresh commands to specific banks while simultaneously handling read/write requests to other banks, thereby reducing the overall impact on productivity.
Solution Approach 2:
The per-bank refresh mechanism enables continuous useful action by allowing the memory controller to maintain read/write operations in active banks while performing refresh operations in separate banks. This continuity ensures that the memory system remains productive throughout the refresh process, minimizing idle time.
3Use of energy by moving object
If per-bank refresh is implemented, then power consumption is reduced and scheduling flexibility is improved, but significant overhead is required in the memory controller to manage refresh commands
Solution Approach 1:
Each bank is equipped with its own refresh counter that autonomously tracks and manages its own refresh operations. This self-service mechanism reduces the burden on the memory controller, as each counter independently generates refresh addresses and tracks refresh status for its associated bank, thereby reducing controller overhead while maintaining per-bank refresh capabilities.
Solution Approach 2:
The segmentation of refresh management into distributed per-bank counters shifts complexity from the central memory controller to individual bank-level components. This distribution reduces the controller's management overhead while enabling fine-grained power management and flexible scheduling.
4Device complexity
If a single refresh counter is used for all banks, then device complexity is reduced, but all banks must be deactivated before refresh operations can proceed
Solution Approach 1:
The invention segments the single refresh counter into multiple per-bank counters, allowing each bank to maintain its own refresh state independently. This enables banks to remain activated during refresh operations of other banks, improving ease of operation and bank activation flexibility while distributing the counter structure complexity across multiple independent units.
Data Source
AI summary
A Dynamic Random Access Memory (DRAM) includes a plurality of banks of memory that can be independently accessed and refreshed, and a plurality of refresh address counters each providing a refresh address to a respective bank. Per-bank refresh commands can be issued to any bank in any order, each refreshing a row in a single bank identified by the respective refresh address counter. An all-bank refresh command can be issued at any time to refresh rows in all banks identified by respective refresh address counters. A per-bank refresh command increments the respective refresh address counter while an all-bank refresh command increments all refresh address counters. Refresh address counters operate independently of each other and do not have to be synchronized in any way.