DRAM Refresh Control Circuit Mitigating Row Hammer
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Solution Overview
Problem
Modern DRAM chips face data corruption issues due to 'row hammer' effects, where activating one row can disturb adjacent rows, especially as feature sizes shrink, leading to data loss if rows are accessed excessively before the next refresh cycle, and existing solutions like Targeted Row Refresh (TRR) require significant time to enter and exit mode, disrupting normal operations.
Innovation Solution
A memory controller with a refresh control circuit that monitors an activate counter to issue refresh management (RFM) commands strategically, only when the counter exceeds an intermediate threshold and is below a maximum threshold, ensuring timely refresh without disrupting ongoing operations, and uses flexible address decoding to spread logical addresses across multiple sub-banks to mitigate row hammer effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Targeted Row Refresh (TRR) mode is entered to prevent row hammer effects, then data corruption is avoided, but substantial time is lost due to mode entry requirements and idle periods
Solution Approach 1:
The patent performs preliminary monitoring of activate command counts and proactively issues refresh management commands before row hammer corruption can occur. The refresh control circuit continuously tracks activate commands and triggers preventive refresh actions based on threshold comparisons, eliminating the need for time-consuming mode transitions by preparing and executing refresh operations in advance.
Solution Approach 2:
The patent introduces a refresh control circuit as an intermediary component that sits between the command queue and the DRAM interface. This intermediary monitors activate command counts, compares them against thresholds, and autonomously issues refresh management commands when needed, thereby preventing row hammer effects without requiring the processor or memory controller to enter special TRR modes.
2Reliability
If frequent refresh operations are performed to prevent row hammer, then data corruption is prevented, but memory access efficiency deteriorates
Solution Approach 1:
The patent dynamically adjusts refresh management parameters by monitoring the activate command count and comparing it against configurable thresholds (intermediate threshold and maximum threshold). When the count exceeds the intermediate threshold, refresh management commands are issued; when it exceeds the maximum threshold, more aggressive actions are taken. This parameter-based adaptive approach ensures refresh operations occur only when necessary, maintaining data integrity while minimizing disruptions to normal memory access efficiency.
3Reliability
If all banks must be idle before entering TRR mode, then row hammer prevention is ensured, but operational disruption increases
Solution Approach 1:
The refresh control circuit autonomously monitors activate command counts and issues refresh management commands without requiring the system to enter a special TRR mode. The circuit independently tracks the activate count for each bank, compares it against thresholds, and triggers appropriate refresh actions, thereby preventing row hammer effects while allowing normal memory operations to continue uninterrupted in other banks.
Data Source
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AI summary
A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.