DRAM Sub-Array Refresh Using Dummy Cells for Charge Leakage
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Solution Overview
Problem
Volatile memory devices, such as DRAM, experience charge leakage over time, necessitating frequent refresh operations that can impact performance and efficiency.
Innovation Solution
Incorporating a dummy cell region within the memory cell array and performing a body refresh operation by writing data '0' to dummy cells and grounding connected bit lines to transfer accumulated holes, along with a temperature-based mechanism to adjust refresh frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to maintain charge in memory cells, then data retention reliability is improved, but performance and efficiency deteriorate due to operational overhead
Solution Approach 1:
The memory device divides the memory cell array into multiple sub-array blocks, each with independent bit lines. The refresh operation is segmented to affect only one sub-array block at a time, allowing other blocks to remain accessible during refresh, thus maintaining overall memory performance while ensuring data retention reliability.
Solution Approach 2:
The refresh operation is implemented as a periodic action targeting specific sub-array blocks in a cyclic manner. By periodically refreshing only the active or recently accessed sub-array blocks rather than all blocks continuously, the patent reduces refresh overhead while maintaining adequate data retention for actively used memory regions.
2Loss of energy
If body refresh operation is performed by grounding bit lines to transfer accumulated holes, then charge leakage is reduced, but device complexity increases due to additional control circuitry
Solution Approach 1:
The body refresh operation utilizes the existing bit line infrastructure and transistor body regions to perform hole transfer. The bit lines themselves serve as the charge transfer path when grounded, eliminating the need for separate dedicated charge transfer circuits. This self-service approach reduces charge leakage while minimizing additional device complexity.
Solution Approach 2:
The bit lines are designed to serve multiple functions: normal read/write operations and charge transfer during body refresh. By grounding the bit lines, they dual-function as both data transmission conduits and charge transfer paths, reducing the need for dedicated refresh circuitry and thereby limiting the increase in device complexity.
3Manufacturing precision
If dummy memory cells are added to enable body refresh operation, then manufacturing precision is improved through better charge management, but device complexity increases due to additional cell structures
Solution Approach 1:
Dummy memory cells are strategically placed in specific regions of the memory cell array where body refresh operations are most beneficial. Rather than uniformly distributing dummy cells throughout the entire array, the patent applies them locally to sub-array blocks that require enhanced charge management, thereby improving manufacturing precision in critical areas while minimizing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces charge leakage and improves memory performance by effectively managing charge accumulation, especially at higher temperatures, offering a simpler and more efficient alternative to prior art approaches.
Implementation Method 1
performing a body refresh operation by writing data '0' to dummy cells and grounding connected bit lines to transfer accumulated holes
Data Source
AI summary
A memory device including: a memory cell array including a plurality of sub-array blocks, wherein the plurality of sub-array blocks include a plurality of word lines and a plurality of bit lines; a command decoder configured to decode a command received from a memory controller and generate a refresh command to control a refresh operation; and a refresh control circuit configured to receive the refresh command from the command decoder, determine a target row address corresponding to a sub-array block based on a number of body refreshes performed on the sub-array blocks, and output the target row address.