DRAM Refresh Handoff Between Multiple Memory Controllers
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Solution Overview
Problem
Managing refresh operations in dynamic random-access memory (DRAM) is complicated due to the need for periodic refreshing of billions of storage cells, especially when multiple controllers access the same DRAM, which can interfere with read and write operations.
Innovation Solution
A memory system with a processing die that includes local memory controllers and demultiplexers to manage refresh operations, allowing multiple modes of refresh management, including independent control by external and internal controllers, with synchronization mechanisms to prevent data loss during mode transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple controllers manage refresh operations for the same DRAM, then refresh coverage is improved, but interference with read and write operations increases
Solution Approach 1:
The patent segments the DRAM into multiple banks, with each bank independently managed by a dedicated memory controller. This segmentation allows refresh operations to be performed on specific banks without interfering with read/write operations on other banks, thus maintaining refresh coverage while reducing operational interference.
Solution Approach 2:
The patent implements dynamic refresh management where memory controllers can adaptively adjust refresh timing and frequency based on actual workload conditions. This dynamic approach allows the system to prioritize refresh operations when memory is less active, minimizing interference with read and write operations while ensuring adequate refresh coverage.
2Reliability
If refresh operations are performed frequently, then data integrity is improved, but performance of read and write operations deteriorates
Solution Approach 1:
The patent implements periodic refresh operations at optimized intervals rather than continuous refreshing. By calculating and executing refresh operations at strategically timed periodic intervals, the system maintains data integrity while minimizing the frequency of refresh interruptions to read and write operations.
Solution Approach 2:
The patent performs preliminary refresh operations on DRAM banks that are not currently active or are less likely to be accessed soon. By proactively refreshing these banks in advance, the system ensures data integrity is maintained while avoiding interference with currently active read and write operations.
3Adaptability or versatility
If mode transitions between external and internal controllers are implemented, then operational flexibility is improved, but risk of data loss increases
Solution Approach 1:
The patent implements feedback mechanisms where memory controllers continuously monitor the state of DRAM banks and the operational mode of the system. During mode transitions, this feedback allows controllers to detect which banks require refresh and coordinate transitions accordingly, ensuring data integrity is maintained while enabling flexible mode changes.
Solution Approach 2:
The patent introduces a coordination mechanism that acts as an intermediary during mode transitions between external and internal controllers. This intermediary coordinates the transition process, ensuring that refresh operations are properly synchronized and no data is lost during the handoff between controllers.
Data Source
AI summary
A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.