Segmented DRAM Refresh Masking for Low-Power Metadata Storage

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Solution Overview

Problem

Semiconductor memories, particularly volatile DRAM, face issues with power consumption due to frequent refresh operations and data deterioration, leading to unrecoverable memory errors.

Innovation Solution

A storage device with a segmented memory architecture, where a first segment enables refresh operations and a second segment masks them, using a cache memory to store metadata and a memory controller to manage data movement based on cache hits and misses, reducing power consumption by disabling refreshes in masked segments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If refresh operation is enabled in all memory segments, then data reliability is maintained, but power consumption increases

Engineering Contradiction:

Improvedata reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The memory device divides the memory array into multiple segments, with each segment independently controllable for refresh operations. This allows selective masking of refresh operations in specific segments based on data presence and access patterns, reducing overall power consumption while maintaining reliability for active data.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different refresh policies are applied to different memory segments based on their specific needs. Segments containing active or modified data maintain normal refresh operations for reliability, while segments with inactive or cached data have refresh operations masked to reduce power consumption.

Inventive Principle:

Principle #3Local quality

2Use of energy by moving object

If refresh operation is disabled in memory segments, then power consumption is reduced, but data deterioration occurs leading to unrecoverable memory errors

Engineering Contradiction:

Improvepower consumptionVSAvoidmemory error recovery

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The cache memory stores metadata (such as valid bit information, dirty bits, or replacement policy data) in advance, allowing the memory controller to predict which memory segments will be accessed and proactively manage refresh operations before data deterioration becomes critical.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from cache hit/miss detection and metadata analysis to dynamically adjust refresh operations. When a cache miss occurs, the system retrieves data from main memory and updates cache status, providing feedback that informs subsequent refresh decisions for related memory segments.

Inventive Principle:

Principle #23Feedback

3Productivity

If cache memory is used to store metadata, then access efficiency is improved, but device complexity increases

Engineering Contradiction:

Improveaccess efficiencyVSAvoidmemory architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The cache memory serves multiple functions: storing frequently accessed metadata for quick lookup, tracking dirty bits for write-back operations, and providing information for refresh policy decisions. This multi-functionality justifies the added complexity by delivering significant performance benefits across multiple operations.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260030163A1Storage device, operating method thereof, and electronic device

Publication Date: 2026.01.29 SAMSUNG ELECTRONICS CO LTD

AI summary

A storage device, an operation method thereof, and an electronic device are disclosed. A storage device includes a main memory comprising a first segment that is not masked and a second segment that is masked, a cache memory configured to store some metadata stored in the main memory, and a memory controller configured to map a physical address of the second segment to a physical address of the first segment in a remap table for dirty metadata to be stored in the second segment in response to a cache miss occurring.