DRAM Refresh-Based Memory Erasure for Secure Deletion

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Solution Overview

Problem

Existing memory erasure techniques in cloud-native micro-services and memory-stressed computation environments are inefficient, causing performance overheads, bandwidth loss, and potential information leakage due to the high computational cost of erasing memory content, especially in scenarios with high service density and frequent instance launches.

Innovation Solution

Implementing a memory device with control circuitry that triggers memory cell erasure during automatic refresh cycles, utilizing an auxiliary memory to manage erase requests and execute the erasure process out-of-band, minimizing performance impact on read/write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory erasure is performed using traditional techniques, then complete data deletion is achieved, but bandwidth loss and performance jitter increase significantly

Engineering Contradiction:

Improvedata deletion securityVSAvoidbandwidth loss

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent merges memory erasure operation with the automatic refresh cycle. The refresh controller integrates the erase function into the existing refresh mechanism, allowing both refresh and erasure to use the same hardware resources and time slots. This consolidation eliminates the need for separate erasure bandwidth channels, thereby reducing overall bandwidth loss while maintaining secure data deletion.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent utilizes the periodic automatic refresh cycles of DRAM to perform memory erasure. Instead of requiring continuous or interruptive erasure operations, the system leverages the already-scheduled periodic refresh intervals to asynchronously erase memory rows. This periodic approach ensures erasure completes without disrupting normal read/write operations and minimizes bandwidth consumption.

Inventive Principle:

Principle #19Periodic action

2Reliability

If memory erasure is performed using traditional techniques, then complete data deletion is achieved, but service disruptions occur due to performance jitter

Engineering Contradiction:

Improvedata deletion securityVSAvoidservice disruption time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by marking memory rows for erasure in advance during the refresh cycle, rather than executing erasure immediately when requested. The refresh controller schedules and prepares erase operations ahead of time, allowing them to execute asynchronously during subsequent refresh cycles. This eliminates blocking and performance jitter, ensuring continuous service operation without disruptions.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuity of useful action by performing erasure operations during the automatic refresh cycles, which are already part of the normal memory operation timeline. Since refresh cycles occur continuously, the erasure function can execute without interrupting read/write operations or service processing. This ensures seamless, non-blocking memory erasure that maintains service continuity.

Inventive Principle:

Principle #20Continuity of useful action

3Speed

If full DDR bandwidth is allocated for memory erasure, then erasure speed is improved, but bandwidth loss and performance overhead increase

Engineering Contradiction:

Improveerasure speedVSAvoidbandwidth loss

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The patent applies universality by making the refresh controller handle both refresh and erasure functions using the same hardware resources. The refresh controller is designed to be multi-functional, accepting either refresh commands or erase commands and routing them appropriately. This eliminates the need for dedicated erasure bandwidth channels, allowing the system to achieve erasure speed without sacrificing bandwidth efficiency.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Loss of energy

If memory erasure is performed during automatic refresh cycles, then bandwidth loss and performance jitter are reduced, but erasure completion time may be extended

Engineering Contradiction:

Improvebandwidth lossVSAvoiderasure completion time

Core Design Contradiction:

Loss of energyVSDuration of action of moving object

Solution Approach 1:

The patent uses periodic action by distributing erasure operations across multiple automatic refresh cycles. Instead of requiring a single long erasure operation, the system breaks down the erasure task into smaller units that can be executed during each refresh cycle. This periodic execution approach reduces bandwidth loss and performance overhead while completing the overall erasure task efficiently through parallel processing across time.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS12614578B2Memory device, a memory module, a computing system, a method for erasing a memory portion of a memory device and a method for generating an erase request

Publication Date: 2026.04.28 INTEL CORP

AI summary

A memory device comprises an input interface configured to receive an erase request indicating a memory portion to be erased and control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.