DRAM Refresh Operation Within Power Down Mode for Lower Current
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Solution Overview
Problem
Existing DRAMs consume unnecessary current when transitioning between power down and power up modes due to activation of internal circuits during self-refresh operations, which compromises data retention and efficiency.
Innovation Solution
A DRAM chip design that allows for a refresh operation to be performed within the power down mode by altering specific command signals, such as command address signal CA[0], without fully exiting and re-entering the power down mode, thereby reducing unnecessary current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DRAM exits from power down mode to perform refresh operation, then data retention is maintained, but current consumption increases due to internal circuit activation
Solution Approach 1:
The patent applies preliminary action by performing the refresh operation while the DRAM is still in the power down mode, before the need to exit and re-enter power down mode arises. The refresh command is submitted during the power down state, allowing the internal circuits to remain inactive while still maintaining data retention, thus avoiding unnecessary current consumption during mode transitions.
2Reliability
If the DRAM enters and exits power down mode for refresh operation, then data retention is ensured, but internal circuits are activated causing unnecessary current consumption
Solution Approach 1:
The patent applies continuity of useful action by maintaining the power down mode state continuously and performing the refresh operation within this state. Instead of transitioning out of power down mode and back in, the refresh command is executed while remaining in power down mode, ensuring continuous energy savings while maintaining data retention capability.
Data Source
AI summary
An example system includes: a memory chip having a plurality of external terminals; and a controller chip coupled to the plurality of external terminals of the memory chip and configured to issue, via some of the plurality of external terminals, a plurality of commands including a power down entry command and a refresh command. The memory chip is configured to: change an operation mode from a normal mode to a power down mode when the power down entry command is issued from the controller chip; perform a refresh operation when the refresh command is issued from the controller chip in the normal mode; and perform the refresh operation when the controller chip brings one of the plurality of external terminals into a first predetermined level in the power down mode.