Periodic DRAM Refresh Scheduling for Predictable Access
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Solution Overview
Problem
The non-deterministic nature of DRAM accesses due to refresh and maintenance cycles introduces unpredictable latency and bandwidth variations, which is undesirable for deterministic computing environments, especially in high-performance tensor processors used for AI applications.
Innovation Solution
Implement a mechanism where the computer system and DRAM controller synchronize their schedules to avoid collisions between DRAM access requests and refresh/maintenance cycles, ensuring mutually exclusive operations to achieve predictable latency and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM is used for primary memory storage, then large capacity and cost-effectiveness are achieved, but access latency becomes non-deterministic due to refresh and maintenance cycles
Solution Approach 1:
The system performs DRAM refresh and maintenance operations in advance during predetermined time windows before they are needed for data access. The compiler schedules memory access requests to occur after refresh operations are completed, ensuring data integrity without requiring waiting periods that would introduce non-determinism.
Solution Approach 2:
The patent divides DRAM into multiple banks and implements independent refresh schedules for each bank. While one bank is being accessed by the processor, other banks can undergo refresh or maintenance operations. This segmentation allows parallel operation of access and refresh/maintenance, eliminating conflicts and ensuring deterministic access latency.
2Reliability
If refresh cycles are performed periodically on DRAM, then data integrity is maintained, but access requests collide with refresh operations causing unpredictable latency
Solution Approach 1:
Refresh operations are scheduled and executed in advance during predetermined time windows before data access is required. The compiler generates code that issues memory access requests only after the associated refresh operations have completed, ensuring both data integrity and deterministic access timing without collision.
3Reliability
If maintenance updates are performed on DRAM controller, then signaling reliability is improved, but system bandwidth decreases due to update duration
Solution Approach 1:
The patent segments maintenance operations to occur on dedicated maintenance channels or during periods when other DRAM banks are being accessed. Multiple DRAM banks can be accessed in parallel while maintenance is performed on a separate bank or channel, maintaining overall system bandwidth while ensuring signaling reliability through periodic maintenance.
4Reliability
If SRAM caches are added to reduce DRAM access variance, then access predictability improves, but system complexity increases
Solution Approach 1:
Instead of adding complex SRAM cache hardware, the patent uses software-based preliminary action where the compiler analyzes and schedules memory access patterns to avoid conflicts with DRAM refresh and maintenance cycles. This approach achieves deterministic access predictability through compilation-time scheduling rather than hardware caching, avoiding increased system complexity.
Data Source
AI summary
When reading and writing DRAM (dynamic random-access memory), the latency and bandwidth is often unpredictable with large variations. One reason is because all the DRAM memory banks require periodic refreshes and maintenance cycles that interrupt these accesses. DRAM refresh and maintenance cycles are synchronized with the read/write accesses in a mutually exclusive manner, hence, preventing the accesses from being interfered with by a refresh or maintenance cycle resulting in predictable latency and bandwidth performance during read/write operations.