DRAM Error Scrub Sequencing Across Refresh Commands
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently performing error check and scrub (ECS) procedures concurrently with refresh operations, leading to potential signaling conflicts and increased bit error rates due to the limited time window of refresh commands.
Innovation Solution
The ECS procedure is segmented into two portions, with the first portion performed during a refresh command to read and correct code words, and the second portion executed during a subsequent refresh command to write corrected data, ensuring completion within the time window and avoiding conflicts with other operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error check and correction operations are performed during refresh commands, then bit error rates are reduced and reliability is improved, but signaling conflicts occur with other memory operations due to limited time windows
Solution Approach 1:
The ECS procedure is divided into two separate portions: an ECS-read portion performed during a first refresh command, and an ECS-write portion performed during a second refresh command. This segmentation allows error checking and correction operations to be distributed across multiple time windows, preventing signaling conflicts with other memory operations while maintaining reliability improvements.
2Use of energy by moving object
If ECS procedure is performed during refresh operations, then power consumption is reduced compared to separate operations, but the time window for correction is limited
Solution Approach 1:
The ECS-read portion is performed during the first refresh command to detect and correct errors before they can accumulate beyond correction capacity. By performing error checking preliminarily during the refresh operation rather than waiting for a separate operation, the system maintains low power consumption while ensuring errors are addressed within the available time window.
3Reliability
If on-die error correction codes are used, then correction capacity is provided, but error rates can exceed correction capacity when refresh operations are not timely
Solution Approach 1:
The memory device performs continuous error checking during refresh operations and uses the results to determine whether correction is needed. This feedback mechanism ensures that errors are detected and corrected while still within the correction capacity of the on-die ECC codes, preventing information loss that would occur if errors accumulated beyond correction capacity.
Data Source
AI summary
Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.