DRAM Row Access Counting During Column Selection
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Solution Overview
Problem
Memory cells connected to frequently accessed word lines experience charge loss due to interference from neighboring lines, necessitating effective management of frequently accessed word lines.
Innovation Solution
A memory device with a bank to store row access counting values and a column control circuit for counting read and write operations, along with command delay and generation circuits, to manage and update row access counts during column selection operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If row access counting operations are performed during column selection operations, then charge loss is reduced and word line management is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The patent combines the row access counting function with the existing column selection operation timing. The column control circuit that already generates column control signals during column selection operations is enhanced to also perform counting read and write operations. This merging approach allows the system to track row access counts without adding completely separate control circuitry, thereby improving charge retention while limiting the increase in device complexity.
Solution Approach 2:
The column control circuit is designed to serve multiple functions: it generates column control signals for normal column selection operations and simultaneously performs row access counting operations. By making the column control circuit multi-functional, the patent avoids the need for dedicated counting circuits, thus improving reliability through accurate counting while minimizing the increase in device complexity.
2Measurement precision
If command delay circuits and signal generation circuits are added to enable counting operations, then row access tracking precision is improved, but manufacturing complexity increases
Solution Approach 1:
The command delay circuit is designed to generate set, write, and reset signals at predetermined timing based on the pre-charge command. By establishing the timing sequence in advance through the delay circuit, the system ensures accurate row access counting without requiring complex real-time control logic. This preliminary timing setup improves measurement precision while keeping manufacturing relatively straightforward as it uses standard delay circuit techniques.
3Productivity
If counting read and write operations are performed during column selection, then productivity is improved through efficient word line management, but device complexity increases due to additional signal generation circuits
Solution Approach 1:
The counting read and write operations are performed periodically during column selection operations, which already occur at regular intervals during memory access. By synchronizing the counting operations with the existing periodic column selection rhythm, the system improves productivity through efficient word line management without requiring continuous operation of additional circuits, thus limiting the increase in device complexity.
Data Source
AI summary
A memory device includes a bank configured to store a row counting value corresponding to the number of times each word line is accessed when an active operation is performed, and a column control circuit configured to perform a counting read operation and a counting write operation during a period in which a column selection operation set by a pre-charge command is performed.