DRAM Row Management by Access Type to Reduce Memory Latency
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Solution Overview
Problem
Existing DRAM row management policies in computer systems often lead to increased memory access latency due to inappropriate timing of row closure, either closing too early causing row idle states or too late leading to row conflicts, affecting bandwidth and efficiency.
Innovation Solution
A memory management method that dynamically adjusts row management policies based on the type of memory access (read or write) and row hit status, using separate indicators for read and write accesses to optimize when to close target rows, thereby improving accuracy and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory row is closed too early, then a row idle state occurs, but memory access latency is increased
Solution Approach 1:
The patent applies dynamics by making the row management policy adjustable and adaptive rather than fixed. The memory controller dynamically selects between different row management policies (first policy for keeping rows open, second policy for closing rows) based on real-time access patterns and hit status, allowing the system to adapt to varying workload characteristics and minimize latency under different conditions
Solution Approach 2:
The patent changes the parameter of row closure timing based on access type. For read accesses, the system uses one closure timing strategy, while for write accesses, it uses a different strategy. This parameter change allows optimization for the specific characteristics of each access type, balancing between keeping rows open for potential hits and closing them to free resources
2Reliability
If a memory row is closed too late, then a row conflict occurs, but memory access latency is increased
Solution Approach 1:
The patent implements feedback by monitoring the hit status of memory rows and using this information to adjust row management decisions. The memory controller observes whether accesses result in hits or conflicts and uses this feedback to dynamically select appropriate row management policies, creating a closed-loop control system that continuously optimizes performance based on actual behavior
Solution Approach 2:
The system dynamically adjusts row closure timing based on observed access patterns and hit status. When conflicts are detected, the system learns to close rows earlier; when hits occur, it learns to keep rows open longer. This dynamic adaptation allows the system to optimize the timing of row closure to avoid conflicts while minimizing idle states
3Device complexity
If a unified row management policy is used for all memory accesses, then device complexity is reduced, but memory access efficiency deteriorates
Solution Approach 1:
The patent segments the row management policy into different strategies for different access types (read vs. write) and different hit statuses. Instead of using a single unified policy, the system divides the management approach into multiple specialized policies that can be selectively applied, improving efficiency by matching the right policy to the right access scenario while keeping each individual policy relatively simple
4Measurement precision
If different row management policies are executed for different memory banks, then manufacturing precision is improved, but device complexity is increased
Solution Approach 1:
The patent applies local quality by allowing different row management policies to be applied to different memory banks based on their specific access patterns and characteristics. Each memory bank can have its own optimized policy selection, enabling precise local optimization without requiring complete reconfiguration of the entire memory system, thus balancing precision with manageable complexity
Data Source
AI summary
A memory management technology may be applied to a computer system including a dynamic random-access (DRAM). According to the memory management technology, a corresponding row management policy may be executed based on an access type of memory access, where the access type of the memory access includes a read access or a write access.