DRAM Row Address Segmentation for Chip Area Reduction
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Solution Overview
Problem
Modern DRAM semiconductor memories face increased area requirements and production costs due to the need for larger memory cell fields and wider control, address, and data lines, despite advances in semiconductor fabrication and circuit design, which occupy a significant proportion of the semiconductor chip area.
Innovation Solution
The proposed solution involves an access method for DRAM that breaks down row addresses into sub-commands and address information, using a command bus and address bus to efficiently combine and transmit these portions, reducing the number of address lines and pin counts, and includes an address combination circuit with a control unit, selector, and column address decoder to manage row and column addresses for read/write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased, then storage capacity is improved, but chip area is increased
Solution Approach 1:
The patent segments the row address into multiple portions (first row address portion, second row address portion, third row address portion) that are transmitted in separate cycles. This segmentation allows the address bus to use fewer bits per cycle (e.g., 8 bits instead of 16), reducing the area required for address lines and control logic while maintaining the ability to address larger memory capacities.
2Quantity of substance
If memory capacity is increased, then storage capacity is improved, but production cost is increased
Solution Approach 1:
By segmenting the address transmission into multiple cycles with fewer bits per cycle, the patent reduces the required width of address buses and control signals. This reduces manufacturing complexity and production costs, as narrower buses require fewer fabrication steps and have lower defect rates.
3Adaptability or versatility
If address lines are widened, then address capability is improved, but chip area is increased
Solution Approach 1:
The patent divides a wide address (e.g., 16-bit row address) into multiple narrower address portions transmitted sequentially. The first row address portion, second row address portion, and third row address portion are sent in separate cycles, allowing the use of narrower address lines that occupy less chip area while still achieving the required address capability.
Solution Approach 2:
The patent adds the time dimension to address transmission by using multiple cycles. Instead of transmitting the complete address in a single cycle through a wide bus, the address is transmitted across multiple time cycles through a narrower bus, effectively trading time for space.
4Productivity
If control devices are increased, then memory operation is improved, but chip area is increased
Solution Approach 1:
The patent segments control signals into multiple cycles, with each cycle receiving a specific row address portion. This segmentation reduces the complexity of control logic required in any single cycle, as the control unit only needs to manage one portion of the address at a time, thereby reducing the area required for control devices.
Data Source
AI summary
An operating method for a dynamic random access memory (DRAM) obtains a plurality of first sub-commands of a first activate command via a command bus, and obtaining a plurality of first address information regarding a plurality of first portions of a first row address of a specific bank via an address bus. Each of the first sub-commands corresponds to an individual first portion of the first row address of the specific bank. The method further combines the first portions of the first row address of the specific bank in response to a specific sub-command of the first sub-commands, so as to obtain a first complete row address; and obtains an access command via the command bus.