DRAM Row Copy via Shared Bitlines to Cut Internal Transfer Time
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Solution Overview
Problem
Conventional DRAM systems require the use of a host microprocessor or memory controller for data copying, leading to inefficient data transfer within DRAM due to the need for multiple stages and prolonged operation times.
Innovation Solution
Implementing a row copy operation within the DRAM die using hardware-based connections to directly transfer data between source and destination rows within the same bank, allowing for both fast and normal row copy modes without the need for external intermediaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data copying is performed through host microprocessor or memory controller, then data transfer can be completed with existing external infrastructure, but data copy time is prolonged to 500 nanoseconds or more
Solution Approach 1:
The patent extracts the data copying function from external components (host microprocessor and memory controller) and relocates it directly into the DRAM die. This is achieved by implementing a row copy operation that transfers data between rows within the same bank internally, eliminating the need for external intermediaries and reducing copy time to 100-200 nanoseconds.
Solution Approach 2:
The patent introduces an internal row copy mechanism as a new intermediary within the DRAM die itself. This internal copy mechanism acts as a dedicated data transfer pathway between source and destination rows, replacing the external host microprocessor/memory controller intermediary and enabling faster direct transfer.
2Productivity
If multiple stages are used for data copying through external components, then data transfer can be performed with existing infrastructure, but data transfer efficiency is reduced
Solution Approach 1:
The patent segments the DRAM bank into source rows and destination rows that can be independently activated. By dividing the data transfer operation into internal row-to-row copying within the same bank, it eliminates the need for multiple external transfer stages involving host microprocessor reading and writing, achieving single-stage internal transfer.
Solution Approach 2:
The patent merges the data reading and writing operations into a single internal row copy operation. Instead of separate external read and write stages through the host microprocessor, the internal row copy mechanism combines both operations into one unified transfer process, doubling the data transfer efficiency.
Data Source
AI summary
A dynamic random access memory employs either or both of a normal row copy operation or a fast row copy operation to copy selected data from a first row of memory to a second row of memory, without transferring the data to an intermediary processor such as a central processing unit or a memory controller. Both operations depend on a concurrent electrical activation of two separate wordlines within a bank of a DRAM. For the fast row copy operation, the two separate wordlines are part of a shared section of a DRAM bank, having shared bitlines. Bit values are copied directly in parallel via common bitlines. For the normal row copy operation, the two separate wordlines are part of a common bank but not a shared section. Bit values are copied in serial via a general input/output bus within the bank.