DRAM Row Hammer Refresh Using Access Count Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Volatile memory devices like DRAM suffer from data loss due to leakage currents and adjacent cell degradation from intensive word-line access, necessitating frequent refresh operations that increase power consumption and overhead, especially with increased capacity.
Innovation Solution
A semiconductor memory device with a row hammer management circuit that counts access times, identifies intensive access rows, and performs internal read-update-write operations to manage row hammer events, reducing overhead by time-multiplexing user data and count data through the same lines and using ECC encoding/decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to prevent data loss from leakage currents and adjacent cell degradation, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent performs preliminary actions by counting access frequencies and identifying potential row hammer victim rows before actual data loss occurs. The refresh control circuit proactively refreshes identified victim rows based on predicted row hammer events, rather than waiting for actual data corruption to happen. This allows targeted refresh operations that maintain reliability while reducing unnecessary power consumption from blanket refresh operations.
Solution Approach 2:
The memory device performs self-service by autonomously monitoring its own access patterns through the row hammer management circuit and autonomously determining which rows need refresh. The system uses its internal resources (access count data, row hammer prediction logic) to identify and refresh vulnerable rows without external intervention, optimizing the balance between reliability and power consumption based on actual usage patterns.
2Reliability
If refresh operations are performed on all memory cell rows to ensure data integrity, then data reliability is improved, but operational overhead increases
Solution Approach 1:
The patent applies local quality by differentiating between normal rows and identified row hammer victim rows. Instead of applying uniform refresh operations across all memory cell rows, the system applies targeted refresh operations only to specific victim rows identified through access pattern analysis. This localized approach maintains data integrity for vulnerable rows while avoiding unnecessary operations on other rows, thereby reducing operational overhead.
Solution Approach 2:
The system performs partial action by refreshing only the subset of rows that are identified as potential row hammer victims, rather than performing excessive actions on all rows. The row hammer management circuit determines a predicted set of victim rows based on access counts, and the refresh control circuit performs hammer refresh operations only on this partial set, reducing the overall operational overhead while maintaining necessary data integrity.
3Adaptability or versatility
If access count data is stored and managed for all memory cell rows to predict row hammer events, then row hammer management capability is improved, but device complexity increases
Solution Approach 1:
The row hammer management circuit performs multiple functions using a unified approach: it counts accesses for all rows, identifies victim rows, predicts row hammer events, and triggers refresh operations. The same circuitry and data structures are used for both normal operation monitoring and row hammer detection, avoiding the need for separate dedicated hardware for each function. This multi-functionality improves row hammer management capability while controlling circuit complexity through resource sharing.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.