DRAM Row Hammer Tracking With Selective Count Increments
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Solution Overview
Problem
Existing DRAM technologies face performance degradation due to row hammer conditions, which are addressed by incrementing an internal counter to track row activations, but this increases row cycle time and adds complexity and cost.
Innovation Solution
Implementing a memory controller that selectively increments the row activation count based on recent access history, allowing for zero or partial increments to reduce row cycle time impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DRAM increments an internal counter for each row activation to track row hammer conditions, then row hammer detection accuracy is improved, but row cycle time increases
Solution Approach 1:
The patent applies partial action by selectively incrementing the row activation count only for certain access patterns rather than every access. The memory controller determines whether to increment based on analyzing access patterns, applying the incrementing action only when necessary for row hammer detection, thereby reducing unnecessary overhead while maintaining detection accuracy.
Solution Approach 2:
The patent changes the parameter of count increment from a fixed value (always increment by 1) to a variable value (increment by 0 or 1 based on access pattern analysis). This parameter change allows the system to adapt the tracking intensity to the actual row hammer risk, reducing row cycle time when full tracking is not needed while maintaining detection capability when risk is present.
2Productivity
If more banks are added to allow parallel DRAM access to offset performance impact, then productivity is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the row hammer tracking overhead from the critical DRAM access path by implementing tracking in the memory controller rather than within the DRAM array itself. This separation allows the DRAM array to operate at full speed while the controller handles the selective counting, avoiding the need for additional banks or complex scheduling to maintain performance.
3Measurement precision
If read-modify-write operations are performed on each activated row to update the count, then row hammer tracking accuracy is improved, but performance degradation increases
Solution Approach 1:
The patent applies partial action by performing read-modify-write operations only selectively rather than on every activated row. The memory controller analyzes access patterns and determines when count updates are necessary, applying the read-modify-write action only in those cases. This reduces the frequency of performance-degrading operations while maintaining accurate tracking when needed.
Solution Approach 2:
The patent changes the update frequency parameter from constant (update every access) to variable (update based on access pattern analysis). This allows the system to maintain high update accuracy when row hammer risk is detected while reducing update frequency to minimal levels when risk is low, thereby improving overall performance without sacrificing tracking accuracy when needed.
Data Source
AI summary
A memory device can internally track row address activates for perfect row hammer tracking, incrementing an activate count for each row when an access command is received for a row. Instead of incrementing the count for each activate, the memory controller can indicate a number greater than one for the memory device to increment the count, and then indicate not to increment the count for subsequent accesses up to the number indicated. The memory controller can determine whether the row address of an activate command is one of N recent row addresses that received the access command. The memory controller can indicate an increment of zero if the row address is one of the N recent addresses, and indicate an increment of a number higher than one if the row address is not one of the N recent addresses.