DRAM Row-Preset Circuitry for Low-Interference Memory Preset
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Solution Overview
Problem
The communication of signals in memory systems, particularly in DRAM devices, consumes a significant portion of power, primarily due to the transmission of data signals, which affects memory bandwidth and performance.
Innovation Solution
A memory system design that integrates local control circuitry and row-preset circuits to manage write-pattern commands, minimizing interference with normal read and write transactions by efficiently presetting memory cells, thus reducing power consumption and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data signals are transmitted for read and write operations, then memory bandwidth and performance are improved, but power consumption increases significantly
Solution Approach 1:
The patent applies preliminary action by presetting memory cells to known states before actual read/write operations. The row-preset circuits prepare memory cells in advance, so that when data transmission is needed, the cells are already in the correct initial state, reducing the need for extensive signal transmission and lowering power consumption while maintaining bandwidth performance
2Reliability
If refresh transactions are performed periodically, then data retention is improved, but memory bandwidth and speed performance deteriorate
Solution Approach 1:
The patent merges refresh transactions with preset operations by combining them into a unified row-preset circuit architecture. The row-preset circuits can perform both refresh operations and preset operations using the same hardware resources, allowing these transactions to be executed simultaneously or in an interleaved manner, thereby maintaining data retention without significantly impacting memory bandwidth
Solution Approach 2:
The patent uses preliminary action by performing preset operations in advance of actual data access. By presetting memory cells before read/write operations, the system prepares the memory structure ahead of time, which allows refresh operations to be scheduled more efficiently and reduces the impact on overall memory performance
3Use of energy by moving object
If row-preset circuits are added to manage write-pattern commands, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent applies universality by designing row-preset circuits that can perform multiple functions: they can execute preset operations, refresh operations, and prepare memory cells for various types of access operations. This multi-functionality reduces the need for separate dedicated circuits for each operation, thereby limiting the increase in device complexity while achieving significant power consumption reduction
Solution Approach 2:
The row-preset circuits are designed to service themselves by automatically managing the preset operations based on command signals from the memory controller. The circuits self-regulate their operation to minimize interference with normal read and write transactions, reducing the need for additional complex control mechanisms
4Use of energy by moving object
If preset operations are performed, then power consumption is reduced, but memory speed performance may be affected
Solution Approach 1:
The patent applies preliminary action by performing preset operations in advance, allowing memory cells to be prepared before actual data access. This pre-preparation reduces the time needed during actual read/write operations, thereby maintaining high memory speed performance while reducing overall power consumption
Solution Approach 2:
The patent uses dynamics by making the preset operation timing flexible and adaptive. The row-preset circuits can dynamically adjust when preset operations occur based on memory access patterns, performing them during idle periods or in advance of predicted access, thereby minimizing impact on memory speed while achieving power savings
Data Source
AI summary
A memory system includes a host controller that issues access commands, including write pattern commands, to a dynamic, random-access memory (DRAM). Local control circuitry and a row-preset circuitry service write-pattern commands to minimize conflict with access transactions, e. In the memory device, local control circuitry and a row-preset circuit service the write-pattern commands in a manner that minimizes interference with normal read and write transactions. Presetting memory to e.g., erase potentially vulnerable data after use is therefore accomplished efficiently and with no or minimal impact on memory bandwidth and speed performance.