DRAM Row Timing Control Using Charge-Aware Access Windows
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Solution Overview
Problem
High DRAM latency in memory systems adversely impacts overall computing device performance, and existing technologies have not effectively addressed this bottleneck.
Innovation Solution
Implement a DRAM access timing control system that tracks recently accessed rows using a highly-charged row table, allowing for the use of reduced timing parameters (tRCD, tRAS) for faster access to recently accessed rows and standard parameters for less recently accessed rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard DRAM timing parameters are used for all row accesses, then timing simplicity is maintained, but DRAM latency increases and memory system performance deteriorates
Solution Approach 1:
The patent applies different timing parameters (tRCD and tRAS) based on the specific characteristics of each row access. Rows that have been recently precharged use shorter timing parameters, while other rows use standard timing parameters. This local differentiation of timing characteristics resolves the contradiction by optimizing performance for specific access patterns without compromising overall system stability.
Solution Approach 2:
The patent dynamically selects timing parameters based on the current state of DRAM rows, specifically whether a row has been recently precharged. The timing parameters are not fixed but adapt according to the access pattern and row state, allowing the system to achieve lower latency when conditions permit while maintaining reliability when conditions do not.
2Speed
If shorter timing parameters are used to reduce DRAM latency, then access speed improves, but timing parameter reliability may be compromised
Solution Approach 1:
Shorter timing parameters are applied selectively only to rows that have been recently precharged and are therefore known to be stable and ready for immediate access. Other rows continue to use standard, more conservative timing parameters. This ensures that speed improvements are achieved only when reliability conditions are met.
Solution Approach 2:
The system performs a precharge operation on a row before attempting to access it with shorter timing parameters. This preliminary action prepares the row in advance, ensuring that the capacitances are charged and the row is stable, thereby making the subsequent use of shorter timing parameters safe and reliable.
3Loss of time
If a table tracking row addresses is implemented to enable selective timing, then DRAM latency is reduced for accessed rows, but device complexity increases
Solution Approach 1:
The patent uses a table to store copies of row addresses that have been recently precharged. This table is a simplified data structure that tracks only the essential information needed for timing optimization (the row address), rather than maintaining complex state information. This approach reduces latency through selective timing while keeping the added complexity minimal.
Solution Approach 2:
The table acts as an intermediary between the precharge/activate commands and the timing parameter selection logic. It provides a simple mechanism to communicate which rows are candidates for shorter timing parameters, decoupling the complexity of timing management from the command execution flow.
Data Source
AI summary
DRAM access timing may be controlled based on charge remaining in cells of a DRAM row. DRAM timing and thus latency may be reduced in instances in which repeated row accesses are directed to the same row within an amount of time during which the row cell capacitances remain highly charged. In response to a row precharge, the row address may be stored in a table. Then, in response to a row activation and subsequent read/write access, a first timing parameter may be used in accessing the row when the row is in the table, and a second timing parameter may be used in accessing the row when the row is not in the table. Entries in the table may be periodically invalidated to reflect charge loss.