DRAM Row Hammer Address Detection With Adjacent Row Refresh
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Solution Overview
Problem
Existing DRAM systems face intermittent failures due to row hammering, where repetitive access to a single row causes decay in adjacent rows, and increasing the number of registers to manage diverse types of row hammers adversely affects DRAM density.
Innovation Solution
A memory device with a row hammer managing circuit that detects row hammer addresses based on pre-existing addresses and input addresses during a monitoring period, and a refresh control circuit that performs refresh operations on adjacent memory cell rows, reducing the need for additional registers by efficiently managing various types of row hammers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of registers is increased to manage diverse types of row hammers, then the ability to defend against various row hammer attacks is improved, but the DRAM density deteriorates
Solution Approach 1:
The patent implements a universal row hammer management mechanism that can handle multiple types of row hammer attacks (including adjacent row hammer, distant row hammer, and multi-pattern row hammer) using a fixed number of registers. The row hammer managing circuit detects different attack patterns and applies appropriate refresh strategies without requiring additional registers for each attack type, thus achieving multi-functionality with limited resources.
Solution Approach 2:
The patent changes the monitoring parameters and detection thresholds based on the detected row hammer pattern. Instead of using separate registers for each attack type, the system dynamically adjusts monitoring periods, refresh frequencies, and detection criteria to adapt to different row hammer scenarios, enabling effective defense with a fixed register configuration.
2Adaptability or versatility
If the number of registers is significantly increased, then more row hammer addresses can be monitored, but the manufacturing complexity increases and DRAM density decreases
Solution Approach 1:
The patent implements dynamic row hammer address monitoring where the monitoring capacity adapts to the actual attack patterns detected. The system dynamically adjusts which addresses are monitored and at what frequency based on real-time detection, rather than statically allocating registers for all possible addresses. This dynamic approach allows the fixed register configuration to effectively monitor a larger address space.
Solution Approach 2:
The row hammer managing circuit automatically detects and responds to row hammer attacks without requiring external intervention or additional control logic. The system self-adjusts its monitoring focus and refresh operations based on the detected attack patterns, enabling the fixed register configuration to effectively handle diverse attack scenarios independently.
Data Source
AI summary
A memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer managing circuit, which is configured to detect a row hammer address based on a pre row hammer address, and each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to a plurality of the rows of memory cells. A refresh control circuit is provided and is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.