One-Transistor DRAM Cell with Asymmetric Junctions
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Solution Overview
Problem
Single-transistor DRAM cells face challenges in achieving sufficient speed for both read and write operations due to inefficient hole removal from the floating body region, leading to issues in accurately distinguishing between '0' and '1' states, especially in large memory arrays.
Innovation Solution
The use of a Schottky junction for efficient hole removal during write operations and an n-p junction during read operations to prevent data loss, with specific voltage biases applied to the source and drain regions to manage carrier accumulation and storage effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single transistor DRAM cell structure is used to achieve high density, then the memory density is improved, but the speed of read and write operations deteriorates due to inefficient hole removal from the floating body region
Solution Approach 1:
The patent applies different junction types at different locations: a Schottky junction is used at one source/drain region for efficient hole removal during write operations, while an n-p junction is used at the other source/drain region to prevent data loss during read operations. This local differentiation of junction properties resolves the speed limitation while maintaining the high-density single-transistor structure.
2Speed
If hole removal is accelerated to improve write speed, then write operation speed is improved, but data loss occurs during read operations
Solution Approach 1:
The patent uses a Schottky junction at one source/drain region to enable fast hole removal for rapid write operations, while an n-p junction at the other source/drain region prevents excessive hole removal during read operations. This spatial differentiation allows the system to achieve both fast write speeds and reliable data retention during reads.
3Speed
If hole/electron pair generation is increased to improve write speed, then write operation speed is improved, but the ability to distinguish between '0' and '1' states deteriorates
Solution Approach 1:
The asymmetric junction configuration enables differential control of carrier dynamics: the Schottky junction region facilitates rapid hole removal for fast writes, while the n-p junction region maintains proper charge balance for accurate state distinction. This local functional differentiation resolves both the speed and precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the robustness of write '0' operations and reduces data loss during read '1' operations, providing a better read margin between '0' and '1' states across the memory array, particularly for outlying bits.
Implementation Method 1
the first source/drain region includes a Schottky diode junction with the body region... the Schottky diode junction removes majority carriers from the body region to write a first state
Implementation Method 2
the second source/drain region includes an n-p diode junction with the body region... the n-p diode junction with the body region
Data Source
AI summary
A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.