DRAM-SCM Hybrid Memory Module Caching for Capacity and Performance

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Solution Overview

Problem

Existing DRAM devices face challenges in scaling capacitive performance and manufacturing costs, while non-volatile memory technologies like RRAM and PCRAM lack the performance of DRAM counterparts.

Innovation Solution

A memory system architecture that integrates DRAM and storage class memory (SCM) components, utilizing a hybrid module with DRAM providing caching functionality for SCM devices, and employing a point-to-point architecture with back channel connections for load balancing and efficient data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If DRAM devices are scaled to increase storage capacity, then device storage capacity is improved, but capacitive performance for charge storage deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidcapacitive performance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent combines DRAM and SCM into a hybrid memory module, where DRAM components provide high-speed caching and SCM components provide non-volatile storage. This merging allows the system to achieve both high storage capacity and reliable charge storage by leveraging the complementary strengths of each memory type.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The DRAM components act as an intermediary between the controller and SCM components, buffering data transfers and managing the interface between volatile and non-volatile memory. This intermediary role enables efficient data movement while maintaining the reliability benefits of SCM and the speed benefits of DRAM.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If non-volatile memory technologies are used, then manufacturing cost is reduced, but performance deteriorates

Engineering Contradiction:
Improvemanufacturing costVSAvoidperformance
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The hybrid memory module applies local quality by assigning different memory types to different functional requirements: DRAM components are used for performance-critical caching operations where speed is paramount, while SCM components are used for capacity-critical storage operations where cost is paramount. This localized optimization resolves the contradiction by matching memory technology to specific performance and cost requirements within the same system.

Inventive Principle:
Principle #3Local quality

3Productivity

If DRAM and SCM are integrated in a hybrid module, then system performance is improved, but device complexity increases

Engineering Contradiction:
Improvesystem performanceVSAvoidmodule complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The hybrid memory module achieves universality by designing a unified interface and control mechanism that can address both DRAM and SCM components through a single memory interface. The controller can transparently manage both memory types using standard memory operations, allowing the complex multi-functional module to be controlled with relatively simple logic and reducing the practical complexity despite the enhanced capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12411781B2Memory system with cached memory module operations
Publication Date: 2025.09.09 RAMBUS INC
  • US12411781B2 patent drawing
  • US12411781B2 patent drawing
  • US12411781B2 patent drawing

AI summary

A memory controller includes an interface to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space. At least a portion of the DRAM storage space is configured as a cache for the SCM storage space. The interface to receive an incoming tag address for a read operation. Tag comparison circuitry performs a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache. The data in the addressed DRAM cache space is selectively provided directly to the memory controller as first read data based on the results of the comparison.