DRAM Segmented Data Lines for On-Chip Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As technology nodes shrink, DRAM devices face challenges in maintaining data reliability due to limited charge storage in capacitors, necessitating improved error correction mechanisms.
Innovation Solution
The introduction of a segmented data line structure with extra bit line sets and data lines that transmit error correction/detection codes, enhancing I/O bandwidth and enabling additional bits for error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If technology nodes are shrunk to reduce device size, then device integration is improved, but capacitor charge storage capacity deteriorates leading to data reliability issues
Solution Approach 1:
The data transmission path is segmented into multiple independent data lines (first data line, second data line, third data line). Each data line can independently transmit different data bits, allowing the system to provide error correction capability by transmitting additional redundancy bits through separate physical paths, thus improving data reliability without increasing capacitor size.
Solution Approach 2:
The patent transitions from a single-data-line architecture to a multi-dimensional data transmission structure by introducing multiple data lines operating in parallel. This dimensional expansion allows simultaneous transmission of multiple data bits including error correction codes, effectively adding redundancy in the spatial dimension to compensate for the reduced charge storage capacity at smaller technology nodes.
2Reliability
If extra data lines are added to transmit error correction codes, then data reliability is improved, but device complexity increases
Solution Approach 1:
The multiple data lines are designed with multi-functionality to serve different purposes under different operating modes. The same data line infrastructure can be used for both normal data transmission and error correction code transmission by controlling the column selection circuit appropriately, reducing the need for completely separate dedicated error correction pathways and thereby limiting the increase in device complexity.
Solution Approach 2:
The column selection circuit is configured to dynamically switch between different data line connections based on the operational mode (normal data reading vs. error correction code reading). This dynamic reconfiguration allows the system to adapt the data transmission path in real-time, enabling error correction functionality without permanently increasing the static structural complexity of the device.
Data Source
AI summary
A memory device includes a first bit line set, a first column selection circuit, a first data line and a second data line. The first bit line set includes a first bit line and a second bit line. The first column selection circuit is coupled to the first bit line and the second bit line. The first data line includes a first line segment coupled to the first column selection circuit. The second data line includes a second line segment coupled to the first column selection circuit. Wherein the first column selection circuit is configured to electrically connect the first bit line to the first line segment for transmitting a first bit of normal data to the first line segment, and to electrically connect the second bit line to the second line segment for transmitting a first bit of Error Correction/Detection data to the second line segment.