DRAM Fault Isolation Through Segmented ECC Prefetch Bits
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Solution Overview
Problem
Conventional memory systems face challenges in increasing memory performance and error correction, particularly with limited hardware space and compatibility issues with different data formats, leading to uncorrectable errors and increased costs.
Innovation Solution
A memory error correction system that groups bit rows within error correction regions to enable correction of multiple bit errors, even in wider I/O interfaces, without adding additional hardware, by using ECC memory blocks to correct errors in 8x8 prefetch bit arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction components are implemented using conventional techniques, then single bit errors can be corrected, but multiple bit errors in wider I/O interfaces (x8, x16) result in uncorrectable errors
Solution Approach 1:
The patent divides the wider data bus (x8, x16) into multiple smaller segments (x4 groups), with each segment processed by a separate ECC component. This segmentation allows each ECC component to handle 4-bit wide data correctly, while collectively covering wider interfaces. The data bus is divided into groups where each group can be independently corrected by dedicated ECC logic.
Solution Approach 2:
The ECC components are designed with multi-functionality to handle both traditional x4 interfaces and wider x8/x16 interfaces through the same correction mechanism. By using the same ECC component type across different interface widths via segmentation, the system achieves universal error correction capability without requiring format-specific correction logic.
2Productivity
If additional memory hardware is added to increase memory performance, then memory capacity increases, but manufacturing costs and power consumption increase
Solution Approach 1:
The patent merges error correction functionality directly into the memory controller logic rather than requiring separate external correction components. The ECC components are integrated within the memory controller, combining control and correction functions in one unit. This integration reduces the need for additional discrete hardware components, thereby lowering manufacturing costs while maintaining enhanced error correction capabilities.
3Productivity
If additional memory hardware is added to increase memory performance, then memory capacity increases, but power consumption increases
Solution Approach 1:
The patent merges error correction functionality directly into the memory controller logic rather than requiring separate external correction components. The ECC components are integrated within the memory controller, combining control and correction functions in one unit. This integration reduces the need for additional discrete hardware components, thereby lowering manufacturing costs while maintaining enhanced error correction capabilities.
4Reliability
If memory blocks use specific formats (x4), then error correction works reliably, but wider interfaces (x8, x16) cannot be corrected
Solution Approach 1:
The patent divides the wider data bus (x8, x16) into multiple smaller segments (x4 groups), with each segment processed by a separate ECC component. This segmentation allows each ECC component to handle 4-bit wide data correctly, while collectively covering wider interfaces. The data bus is divided into groups where each group can be independently corrected by dedicated ECC logic.
Data Source
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AI summary
The present disclosure relates to systems, methods, and computer readable media for implementing fault isolation in memory without incurring a die size penalty. For example, systems disclosed herein may involve identifying row addresses for sub-word line drivers accessing data from a memory block (e.g., a dynamic random-access memory (DRAM) block of memory). The systems disclosed herein may further serialize or otherwise compile bit rows into a prefetch bit including a pattern of bits. In generating the prefetch bit, the systems described herein may selectively group bits of data into respective regions that enable an error correction scheme to be applied to the pattern of data while minimizing a likelihood of uncorrectable errors within the prefetch bit.