One-Transistor DRAM Cell Noise Reduction via Segmented Gate
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The one-transistor type DRAM memory cell with no capacitor experiences significant capacitive coupling between the word line and the floating body, leading to noise in data reading and writing, resulting in incorrect data storage and retrieval, and poses challenges in achieving high integration and performance.
Innovation Solution
A memory device with a semiconductor element structure that includes multiple gate conductor layers and impurity layers, where voltages are controlled to manage positive hole groups generated by impact ionization, allowing for improved data holding and erasing operations, and utilizing separate gate capacities to minimize noise and enhance reading and writing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a one-transistor type DRAM memory cell with no capacitor is used, then high integration is achieved, but significant capacitive coupling between the word line and floating body causes noise in data reading and writing
Solution Approach 1:
The gate conductor layer is divided into multiple segments (first gate conductor layer and second gate conductor layer) separated by an insulating layer. This segmentation reduces the capacitive coupling between the word line and the floating body by interrupting the direct electrical field interaction, thereby reducing noise while maintaining high integration density.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the first gate conductor layer and the second gate conductor layer. This insulating layer acts as a mediator that reduces the capacitive coupling effect between the word line and the floating body, eliminating noise without sacrificing the compact structure needed for high integration.
2Object-affected harmful factors
If multiple gate conductor layers are introduced to reduce noise, then capacitive coupling noise is reduced, but device structure becomes more complex
Solution Approach 1:
The multiple gate conductor layers serve multiple functions: the first gate conductor layer provides primary gate control, the second gate conductor layer provides additional control for noise reduction, and together they enable independent voltage adjustment to manage positive hole groups. This multi-functionality justifies the increased structural complexity by delivering both noise reduction and enhanced data operation control.
3Reliability
If voltages are controlled to manage positive hole groups, then data holding and erasing operations are improved, but control complexity increases
Solution Approach 1:
The voltage applied to the gate conductor layers is made dynamic and adjustable rather than fixed. By independently controlling the voltages on the first and second gate conductor layers, the system can dynamically manage positive hole groups during different operations (writing, holding, erasing), improving data storage reliability while adapting to different operational states.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise during data operations, increases the potential difference margin between '1' and '0' states, and enhances the performance and densification of the DRAM memory cell, enabling more reliable and efficient data storage.
Implementation Method 1
a first gate insulating layer that covers both side surfaces of the first semiconductor layer close to the first impurity layer in a second direction parallel to the substrate and vertical to the first direction; a first gate conductor layer and a second gate conductor layer that cover both side surfaces of the first gate insulating layer in planar view and that are separated from each other
Data Source
AI summary
In a memory device, pages are arrayed in a column direction on a substrate, each page constituted by memory cells arrayed in row direction on a substrate. Each memory cell includes a zonal P layer. N+ layers continuous with a source line and a bit line respectively are on both sides of the P layer. Gate insulating layers surround part of the P layer continuous with the N+ layer and part of the P layer continuous with the N+ layer, respectively. One side surface of the gate insulating layer is covered with a gate conductor layer continuous with a first plate line, and the other side surface is covered with a gate conductor layer continuous with a second plate line. A gate conductor layer continuous with a word line surrounds the gate insulating layer.