DRAM Access Transistor Layout for Selective Cell Coupling
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Solution Overview
Problem
Conventional DRAM architectures access all memory cells along a row when a wordline is activated, making it difficult to selectively access specific memory cells or individual cells, leading to inefficiencies in power consumption and data handling.
Innovation Solution
The integration of secondary access devices between primary access devices and digit lines allows for selective coupling of digit lines to specific memory cells along an activated row, enabling controlled access to individual memory cells by switching both primary and secondary access devices to their ON modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional DRAM architecture is used with wordline activation, then all memory cells along a row are accessed, but this causes high power consumption and inability to selectively access specific cells
Solution Approach 1:
The access path is segmented into two stages: primary access devices (first transistors) that connect memory cells to digit lines, and secondary access devices (second transistors) that connect digit lines to sense amplifiers. This segmentation allows selective activation of only the necessary access paths, enabling individual cell access while reducing power consumption compared to conventional row-wide activation.
Solution Approach 2:
Digit lines serve as intermediary elements between the primary access devices and sense amplifiers. The secondary access devices (second transistors) act as intermediaries that selectively couple digit lines to sense amplifiers based on the target memory cell address, enabling precise cell selection without activating the entire row.
2Productivity
If all memory cells along a row are accessed simultaneously, then data handling is simplified, but efficiency and power consumption deteriorate
Solution Approach 1:
The memory access system dynamically configures the access path based on the target memory cell address. The secondary access devices are selectively activated to create dynamic access paths from specific memory cells through digit lines to sense amplifiers, allowing efficient data handling for individual cell access while maintaining the ability to handle multiple cells when needed.
3Ease of operation
If secondary access devices are added between digit lines and primary access devices, then selective cell access is enabled, but device complexity increases
Solution Approach 1:
The secondary access devices are merged with the existing digit line structure, allowing the same digit lines to serve both conventional row-access operations and new selective cell-access operations. This merging approach enables selective access functionality without completely redesigning the memory array architecture, thus limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces power consumption by allowing selective access to specific memory cells, enabling a common sense amplifier to be shared among multiple digit lines and improving data handling efficiency compared to conventional methods.
Implementation Method 1
The secondary access devices may be utilized to selectively couple the digit lines to only specific memory cells along an activated row
Implementation Method 2
an electrical field generated by voltage along the wordline may gatedly couple the bitline to the capacitor during read/write operations
Data Source
AI summary
Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.