DRAM Self-Correction Low Power Refresh
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) systems face high power consumption due to frequent refresh and error correction operations, which is a drawback for low power applications, especially in embedded systems and battery-powered devices.
Innovation Solution
The integration of low power self-refresh and self-correction capabilities in DRAM arrays, allowing for combined operations that reduce read and write accesses, and selective partial write-backs only when errors are detected, thereby minimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed on DRAM cells to prevent data loss, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent segments the DRAM array into multiple banks, allowing selective refresh of only those banks that contain dirty pages (modified data). This segmentation enables the system to refresh a fraction of the total memory at any given time, significantly reducing power consumption compared to refreshing the entire array, while still maintaining data reliability for modified pages.
Solution Approach 2:
Instead of performing full refresh operations on entire DRAM rows or the complete array, the patent implements partial refresh by targeting only the specific banks and pages that require refreshing. This partial action approach reduces the number of activated word lines and bit lines, thereby reducing dynamic power consumption while ensuring data integrity for the necessary pages.
2Reliability
If error detection and correction operations are performed separately from regular read/write operations, then error correction capability is improved, but latency increases
Solution Approach 1:
The patent merges error detection and correction operations with regular read/write operations into a unified process. When data is read from DRAM, the same read path is used to retrieve both the data and its associated error correction code (ECC). The ECC is immediately processed to detect and correct errors before the data is returned to the processor, eliminating separate error correction latency and making the process transparent to the processor.
3Reliability
If complete row read-out and write-back is performed for every refresh operation, then data integrity is improved, but power consumption increases
Solution Approach 1:
The patent extracts and processes only the essential information needed for refresh decisions - specifically, the dirty page bit status for each bank. By extracting this control information separately from the actual data refresh operation, the system can make informed decisions about which banks require refreshing without performing unnecessary read-out and write-back operations on clean pages, thereby reducing power consumption while maintaining data integrity.
Data Source
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AI summary
Apparatuses and methods for low power combined self-refresh and self-correction of a Dynamic Random Access Memory (DRAM) array. During a self-refresh cycle, a first portion of a first row of the DRAM array is accessed and analyzed for one or more errors, wherein a bit width of the first portion is less than a bit width of the first row. If one or more errors are detected, the one or more errors are corrected to form a corrected first portion. The corrected first portion is selectively written back to the first row. If no errors are detected in the first portion, a write back of the first portion to the first row is prevented.