DRAM Self-Initialization Using Stored Access Parameters

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Solution Overview

Problem

Conventional DRAM initialization methods rely on external controllers like CPUs, leading to high latency, bandwidth consumption, and power usage due to large data transfers, necessitating more efficient approaches.

Innovation Solution

A memory device with a memory controller, non-volatile memory, and preloader that flushes and corrects access parameters within the device, reducing initialization time by releasing CPU resources and utilizing an additional processor for calibration and correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If external controller (CPU) performs initialization operations, then initialization can be performed, but large amounts of data must be communicated back and forth consuming high bandwidth and power

Engineering Contradiction:
Improveinitialization speedVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent extracts the initialization function from the external CPU controller and relocates it to an internal processor within the memory device. This allows the memory device to perform self-initialization using stored access parameters, eliminating the need for large data transfers between CPU and memory, thereby significantly reducing power consumption and initialization time.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The memory device performs self-initialization by using access parameters that are pre-stored in its internal storage device. The internal processor reads these parameters and configures the memory array without requiring continuous external control or data transfer, enabling the system to serve itself during initialization and reducing overall power consumption.

Inventive Principle:
Principle #25Self-service

2Productivity

If external controller (CPU) performs initialization operations, then initialization can be performed, but initialization causes high latency as large amounts of data are transferred over the memory bus

Engineering Contradiction:
Improveinitialization speedVSAvoidinitialization latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent extracts the initialization function from the external CPU controller and relocates it to an internal processor within the memory device. This allows the memory device to perform self-initialization using stored access parameters, eliminating the need for large data transfers between CPU and memory, thereby significantly reducing power consumption and initialization time.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The access parameters are pre-stored in the memory device's internal storage device before initialization is needed. When initialization occurs, the internal processor simply reads these pre-prepared parameters rather than receiving them through time-consuming external data transfers, thereby reducing initialization latency.

Inventive Principle:
Principle #10Preliminary action

3Loss of time

If access parameters are flushed to storage device and corrected, then initialization time is reduced, but additional processor resources are required for calibration and correction

Engineering Contradiction:
Improveinitialization timeVSAvoidprocessor resources
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent extracts the initialization function from the external CPU controller and relocates it to an internal processor within the memory device. This allows the memory device to perform self-initialization using stored access parameters, eliminating the need for large data transfers between CPU and memory, thereby significantly reducing power consumption and initialization time.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12481581B2Apparatus and method thereof for dram initialization
Publication Date: 2025.11.25 MEDIATEK INC
  • US12481581B2 patent drawing
  • US12481581B2 patent drawing
  • US12481581B2 patent drawing

AI summary

An apparatus is provided herein, which includes a memory device. The memory device includes a memory array, a storage device, and a memory controller. The storage device stores access parameters corresponding to a plurality of access modes. The memory controller accesses the memory array with the access parameters corresponding to one of the access modes. When the memory device is booted up, the memory controller flushes the access parameters corresponding to each of the access modes to the storage device.