DRAM Self-Refresh ECC for Low-Power Data Retention
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) devices consume significant power, especially during self-refresh modes, leading to reduced battery life in portable devices and increased heat generation, and existing methods to reduce power consumption either result in data loss or are inefficient.
Innovation Solution
Implementing error correction coding (ECC) and Auto Temperature Compensated Self Refresh (ATCSR) to reduce refresh rates while employing partial ECC cycles during low-power modes, allowing for detection and correction of potential errors in DRAM memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the refresh rate is reduced to lower power consumption during self-refresh modes, then power consumption is reduced, but data integrity is compromised and errors occur
Solution Approach 1:
The patent applies preliminary action by performing ECC encoding before the DRAM enters prolonged low-power mode. Check bits are generated and stored in a separate storage location before power reduction occurs. This pre-computed error correction data remains valid even when refresh rates are reduced, allowing error correction without requiring frequent refreshes during low-power operation.
Solution Approach 2:
The patent introduces an intermediary storage location for check bits that is separate from the main DRAM array. This intermediary storage maintains the validity of error correction data independently of the reduced refresh cycle, acting as a mediator that allows the system to operate with lower refresh rates while preserving data integrity through ECC.
2Reliability
If the refresh rate is increased to maintain data integrity, then data integrity is maintained, but power consumption increases significantly
Solution Approach 1:
The patent segments the error correction process into two phases: a full ECC encoding phase performed before entering low-power mode, and a reduced-phase operation during low-power mode where only partial refreshes are needed. This segmentation allows the system to perform comprehensive error correction upfront, then operate with reduced refresh requirements during prolonged low-power periods.
Solution Approach 2:
The patent applies partial action by performing only the necessary minimum refresh operations during prolonged low-power mode, rather than full refresh cycles. Since ECC check bits are already computed and stored, the system only needs to perform partial refreshes to maintain data integrity, significantly reducing power consumption while still preventing data loss.
3Duration of action of moving object
If DRAM devices operate in prolonged low-power modes, then battery life is extended, but errors may occur due to insufficient refresh operations
Solution Approach 1:
The patent prepares error correction data in advance by performing full ECC encoding before entering prolonged low-power mode. This preliminary action ensures that check bits are valid and can be used to detect and correct errors even when refresh operations are minimized during battery-saving operation.
Solution Approach 2:
The patent implements feedback through the ECC decoding process that occurs when exiting low-power mode. The system reads stored data and check bits, decodes them to detect any errors that occurred during low-power operation, and corrects errors if present. This feedback mechanism ensures data integrity is maintained while allowing extended low-power operation.
Data Source
AI summary
Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode.