DRAM Self-Refresh Entry Control for Write and ECC Consistency

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Solution Overview

Problem

Dynamic random access memory (DRAM) systems face race conditions during self-refresh mode entry, leading to mismatches between data and error-correcting code metadata due to incomplete write transactions.

Innovation Solution

Implement polling circuitry and registers to detect and prevent DRAM self-refresh mode entry until write transactions are fully completed, ensuring both data and metadata are stored before transitioning to self-refresh.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If DRAM enters self-refresh mode to save power during idle periods, then power consumption is reduced, but race conditions may occur causing mismatches between data and ECC metadata

Engineering Contradiction:

Improvepower consumptionVSAvoiddata integrity

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by checking the completion status of write transactions before allowing entry into self-refresh mode. The polling circuitry proactively monitors write buffers to ensure all data and metadata writes are finalized before the DRAM transitions to self-refresh, preventing race conditions from occurring in the first place.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary polling circuitry that acts as a mediator between the write transaction completion status and the self-refresh mode entry decision. This intermediary component monitors the write buffer status and controls the transition to self-refresh only when writes are complete, ensuring data integrity while enabling power savings.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the DRAM controller writes both data and ECC metadata to the DRAM array, then data integrity is maintained, but write transactions take longer to complete increasing the window for race conditions

Engineering Contradiction:

Improvedata integrityVSAvoidwrite transaction completion time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements feedback by continuously monitoring the completion status of write transactions through polling circuitry. The system receives feedback about whether data and metadata writes are complete and uses this information to control entry into self-refresh mode, ensuring that the longer write transaction time does not compromise data integrity.

Inventive Principle:

Principle #23Feedback

3Use of energy by moving object

If the DRAM enters self-refresh mode before write transactions are complete, then power is saved sooner, but mismatches occur between data and ECC metadata

Engineering Contradiction:

Improvepower consumptionVSAvoiddata and metadata consistency

Core Design Contradiction:

Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250391458A1Managing race conditions for dram self-refresh

Publication Date: 2025.12.25 QUALCOMM INC

AI summary

Aspects of entry into self-refresh mode by a dynamic random-access memory (DRAM) may be managed using one or more polled registers. Indications of DRAM write activity by the DRAM or a DRAM client may be stored in the registers. The registers may be polled after entry into DRAM self-refresh mode is initiated. The DRAM's entry into self-refresh mode may not be allowed until the registers indicate absence of DRAM write activity.