DRAM Built-In Self-Test with Internal Initialization Patterns
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing amount of memory in computer systems requires extensive data transmission during memory testing, leading to significant heat generation and time consumption, as existing methods rely on processor involvement for built-in-self-test (BIST) and initialization processes.
Innovation Solution
The Dynamic Random Access Memory (DRAM) is equipped with a multipurpose register to perform self-testing using BIST patterns and optional INIT patterns, allowing for self-contained testing and initialization without CPU intervention, thereby reducing data transmission and heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor performs BIST by loading and reading all memory locations through extensive data transmission, then memory errors can be detected, but significant heat is generated and the process consumes excessive time
Solution Approach 1:
The memory device performs self-testing by generating BIST patterns internally and comparing read data with expected patterns without requiring continuous processor involvement. The memory device autonomously executes the test sequence, reducing the time the processor needs to be engaged and minimizing data transmission requirements.
Solution Approach 2:
The BIST pattern generation and comparison functions are extracted from the processor and implemented within the memory device itself. This allows the memory device to perform testing independently, reducing the computational burden and data transmission requirements on the processor.
2Reliability
If the processor performs BIST with extensive data transmission between processor and memory, then memory locations can be tested, but significant heat is generated
Solution Approach 1:
The memory device autonomously generates BIST patterns and performs comparisons internally, minimizing data transmission between the processor and memory. This reduction in data transmission directly reduces the heat generated during the testing process while maintaining comprehensive memory coverage.
Solution Approach 2:
The testing process is segmented into phases where the memory device handles pattern generation and comparison internally, rather than requiring continuous data exchange with the processor. This segmentation reduces the overall data transmission volume and associated heat generation.
3Reliability
If extensive data transmission is used to test large amounts of memory, then all memory locations can be checked, but the communication bandwidth becomes a significant limitation
Solution Approach 1:
The memory device independently generates BIST patterns and performs comparisons without requiring the processor to load patterns or read results for each memory location. This self-service approach eliminates the bottleneck of processor-memory communication bandwidth while maintaining comprehensive testing coverage.
Solution Approach 2:
The BIST patterns are generated and prepared within the memory device before the actual testing begins, rather than being loaded from the processor during testing. This preliminary preparation of test data within the memory device reduces the communication bandwidth requirements during the critical testing phase.
Data Source
AI summary
A method for self-contained testing within a DRAM comprises the DRAM receiving an instruction from an external processor to test a memory core on the DRAM, and the DRAM self-testing the memory core with one or more BIST pattern stored in a multipurpose register on the DRAM. Optionally, the step of self-testing may include writing the BIST pattern into all locations of the memory core, reading each location of the memory core, and comparing the content read from each location of the memory core with the BIST pattern, wherein a negative comparison indicates a failure has occurred. In a further option, the method may further comprise, after testing the DRAM, initializing the DRAM with an INIT pattern stored in the multipurpose register on the DRAM.