DRAM Shared Bitline Sense Amplifier for Latency and Power
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Solution Overview
Problem
Existing DRAM technologies prioritize density over access latency and refresh overhead, leading to suboptimal performance in data centers with low memory utilization.
Innovation Solution
A DRAM structure that includes a bitline sense amplifier shared by adjacent mats, allowing for dynamic switching of unused capacity to improve latency and power consumption, while minimizing area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM density is increased, then storage capacity is improved, but access latency increases and remains high
Solution Approach 1:
The DRAM is divided into multiple independent mats (first mat, second mat, third mat, fourth mat), each with its own cell arrays and bitline sense amplifiers. This segmentation allows parallel access to different mats, reducing overall access latency while maintaining high storage capacity through the combined capacity of all mats.
Solution Approach 2:
The patent introduces a new dimensional organization by arranging mats in a two-dimensional layout (first mat adjacent to second mat, third mat adjacent to fourth mat) with shared bitline sense amplifiers between adjacent mats. This spatial arrangement enables simultaneous access to multiple mats through shared amplifiers, improving access latency without sacrificing density.
2Reliability
If refresh operations are performed frequently, then data reliability is maintained, but power consumption increases
Solution Approach 1:
The patent implements different update cycles for different mats: the first and second mats use a first update cycle, while the third and fourth mats use a second update cycle that is longer than the first. This periodic action with varying periods allows the system to maintain data reliability across all mats while reducing the overall refresh frequency and power consumption, especially for mats that may not require as frequent updates.
3Speed
If dedicated bitline sense amplifiers are assigned to each mat, then access speed is improved, but area overhead increases
Solution Approach 1:
Adjacent mats (first mat and second mat, third mat and fourth mat) share common bitline sense amplifiers. This merging of resources allows the same sense amplifier to serve multiple mats, reducing the total number of sense amplifiers required and thereby reducing area overhead while still enabling parallel access operations that maintain high access speed.
Solution Approach 2:
The bitline sense amplifiers are designed to be universal, serving multiple functions by being shared between adjacent mats. A single sense amplifier can amplify signals from bitlines of different mats, making the amplifier multi-functional and reducing the overall component count and area required in the DRAM structure.
Data Source
AI summary
There is provided a DRAM including a plurality of mats composed of cell arrays, comprising: a first mat including a first cell array that is aligned by first bitlines and first wordlines; a second mat including a second cell array that is adjacent to the first mat and aligned by second bitlines and second wordlines; and a bitline sense amplifier shared by the first bitlines of the first mat and the second bitlines of the second mat, wherein the bitline sense amplifier connected to the first mat is shared only with the second mat.