3D DRAM Cell Structure With Shared Electrode Horizontal Capacitors
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Solution Overview
Problem
The existing vertical transistor structure in dynamic random access memory (DRAM) devices experiences increased contact resistance and negatively affects the film forming quality of high-K dielectric layers due to ion implantation or metal silicide formation, leading to poor electrical properties and yield.
Innovation Solution
A semiconductor structure with horizontal capacitors and transistors is developed, where capacitors are formed on capacitor support structures with shared second electrodes, avoiding the issues of ion implantation and metal silicide formation, and allowing for improved electrical properties and production yield by reducing contact resistance and enhancing film quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation or metal silicide formation is used to form the source, then the transistor structure is completed, but the contact resistance between the capacitor and the source increases
Solution Approach 1:
The patent extracts the problematic source formation steps (ion implantation and metal silicide formation) from the fabrication process. Instead of forming a separate source region through these processes, the invention uses the second semiconductor layer directly as the source, eliminating the need for these harmful processes and thereby reducing contact resistance.
Solution Approach 2:
The second semiconductor layer serves multiple functions: it acts as both the source region for the transistor and as a structural component for capacitor formation. This multi-functionality eliminates the need for separate source formation processes, reducing contact resistance while simplifying the manufacturing process.
2Reliability
If ion implantation or metal silicide formation is used to form the source, then the transistor structure is completed, but the film forming quality of the high-K dielectric layer deteriorates
Solution Approach 1:
The patent removes the harmful ion implantation and metal silicide formation processes from the fabrication sequence. By using the second semiconductor layer directly as the source, the process eliminates contamination and damage to the substrate surface, thereby improving the film forming quality of subsequent high-K dielectric layers.
Solution Approach 2:
The second semiconductor layer is prepared in advance as part of the stacked structure before capacitor formation. This preliminary preparation ensures a clean, undamaged surface that is ready for high-quality dielectric layer deposition, improving film forming quality without requiring additional processing steps.
3Productivity
If vertical transistor structure is used, then the device density is improved, but the contact resistance and film forming quality issues occur
Solution Approach 1:
The patent transitions from a conventional vertical transistor structure to a three-dimensional stacked structure where the second semiconductor layer extends horizontally to form both the source and capacitor support. This dimensional change maintains high device density while eliminating the contact resistance and film forming quality issues associated with vertical structures.
Solution Approach 2:
The capacitor structure is nested within the three-dimensional configuration, with the second semiconductor layer serving as both the transistor source and the capacitor support. This nested arrangement achieves high device density without compromising electrical properties, as the source region is formed without harmful processes.
Data Source
AI summary
Embodiments relate to a semiconductor structure and a fabrication method thereof The method for fabricating a semiconductor structure includes: providing a substrate, where a semiconductor stacked structure formed by alternately stacking first semiconductor layers and second semiconductor layers is formed on the substrate; patterning the semiconductor stacked structure to form cell structures extending along a first direction and arranged at intervals; removing a part of the first semiconductor layers positioned in first regions in the cell structures, such that a part of the second semiconductor layers positioned in the first regions form capacitor support structures; and forming capacitors on exposed surfaces of the capacitor support structures, where the capacitors include first electrodes, dielectric layers and second electrodes sequentially stacked along a direction distant from the capacitor support structures; and all the capacitors in the first regions share the same second electrode.