Capacitor-less 1T DRAM Using SiGe Hetero-junctions
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Solution Overview
Problem
Conventional 1T DRAM cells face challenges in scaling down due to the need for new materials and complex structures, and they struggle with data retention and writing speed, especially as device feature sizes shrink.
Innovation Solution
The use of a memory device with a body region of one semiconductor material sandwiched between source and drain regions of another material, where the semiconductor materials are lattice matched and have different energy gaps, allowing for improved data retention through band offset mechanisms, and the application of specific voltages to write status indications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional 1T DRAM cell structure is used, then the cell size is relatively small and operation speed is relatively high, but new materials such as high dielectric constant film are needed for stacked capacitor or high aspect ratio trench is required for trench capacitor as device feature size shrinks
Solution Approach 1:
The patent extracts the capacitor component from the conventional 1T/1C DRAM cell structure, transitioning to a capacitor-less 1T DRAM design where the floating body of the PMOS transistor serves as the storage node, eliminating the need for separate capacitor structures and associated manufacturing complexities
Solution Approach 2:
The patent changes the material parameter by using silicon-germanium (SiGe) with a smaller energy gap in the drain region compared to silicon in the body region, creating a hetero-junction that provides band offset to constrain carrier leakage and improve data retention without requiring new high dielectric constant materials
2Quantity of substance
If device feature size is shrunk, then integration density increases, but new materials such as high dielectric constant film may be needed for stacked capacitor
Solution Approach 1:
The patent changes the energy gap parameter of the semiconductor material by introducing silicon-germanium (SiGe) in the drain region, which has a smaller energy gap than silicon, creating a hetero-junction that provides natural band offset to constrain carrier leakage and improve data retention
Solution Approach 2:
The patent uses a composite material structure combining silicon body region with silicon-germanium drain region, leveraging the different energy gap properties of these lattice-matched materials to create a hetero-junction that improves carrier confinement without requiring new high dielectric constant materials
3Ease of manufacture
If capacitor-less 1T DRAM is used, then process compatibility with logic devices is improved, but data retention and writing speed may be insufficient
Solution Approach 1:
The patent changes the energy gap parameter by using silicon-germanium (SiGe) with a smaller energy gap in the drain region compared to silicon in the body region, creating a hetero-junction that provides band offset to constrain carrier leakage and improve data retention
Solution Approach 2:
The patent employs a composite material structure with silicon body and silicon-germanium drain regions, utilizing the hetero-junction formed by these lattice-matched materials with different energy gaps to improve carrier confinement and data retention while maintaining process compatibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data retention by constraining electron or hole leakage through hetero junctions, improving the reliability and efficiency of writing operations in 1T DRAM cells.
Implementation Method 1
one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other
Data Source
AI summary
Disclosed is a memory device and method of operation thereof. The memory device may include a source region and a drain region of a first dopant type, the source and drain regions contain a first semiconductor material; a body region of a second dopant type, the body region being sandwiched between the source and drain regions, the body comprising a second semiconductor material; a gate dielectric layer over at least the body region; and a gate comprising a conductive material over the gate dielectric layer. Specifically, one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other of the first semiconductor material and the second semiconductor material.