DRAM Control via Simultaneous Bidirectional Memory Interfaces
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Solution Overview
Problem
Existing systems face challenges in efficiently managing concurrent read and write operations between computing devices and memory devices, leading to delays, buffer inefficiencies, and complex circuitry requirements.
Innovation Solution
The system maintains queues and buffers for read and write operations on the memory device, allowing concurrent execution of read and write commands without requiring complex ordering or buffering circuitry on the computing device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read operations are performed on the memory device, then data can be retrieved from memory, but write operations must be delayed and buffered on the computing device
Solution Approach 1:
The patent segments the communication interface into separate bidirectional channels, allowing read and write operations to be independently managed and executed simultaneously without interfering with each other
Solution Approach 2:
The patent introduces a temporal dimension by implementing simultaneous bidirectional operations, transforming the sequential read-write process into a parallel process that occurs in the same time dimension
2Reliability
If buffers are maintained on the computing device to handle concurrent read and write operations, then operation ordering can be managed, but device complexity and buffer space requirements increase
Solution Approach 1:
The patent extracts the buffering function from the computing device and relocates it to the memory device, eliminating the need for complex buffering circuitry on the computing device while maintaining reliable operation ordering
Solution Approach 2:
The memory device provides self-service by implementing its own buffering and ordering mechanisms, freeing the computing device from the burden of managing complex buffering circuitry and reducing overall system complexity
3Reliability
If separate time slots are reserved for read and write operations on the communication link, then operation conflicts are avoided, but communication efficiency decreases
Solution Approach 1:
The patent implements dynamic bidirectional communication where the communication link can flexibly switch between read and write directions on different channels simultaneously, maximizing communication efficiency while avoiding conflicts through controlled bidirectional access
Data Source
AI summary
A computing device performs both read/write operations concurrently to a memory. Queues for read or write operations are maintained on the memory, allowing the computing device to issue concurrent read/write commands, without complex ordering/buffering circuitry. For a read operation, the memory receives the read command and buffers it in a priority order assigned thereto. The memory can perform the read command and respond with the requested response on a data bus disposed to communicate read data. For a write operation, the memory receives the write command and buffers it for processing in a priority order for that command, such as for relatively immediate processing. The memory can perform the write command using write data on a separate data bus disposed to communication write data.