DRAM Output Driver Slew Rate Calibration for PVT Variations
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Solution Overview
Problem
Semiconductor device manufacturing faces challenges due to variations in process, voltage, and temperature (PVT) conditions, leading to inconsistent device performance and increased costs as more products need to be produced to account for unusable devices, necessitating effective control circuitry to maintain performance specifications.
Innovation Solution
A slew rate control circuit is implemented, which includes a voltage regulation circuit and a calibrator that adjusts the drive strength of pre-drivers through a feedback loop, using a network of transistors and resistors to compensate for PVT variations, ensuring consistent output signal integrity by monitoring and adjusting channel conduction strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If different device geometries and process variations are used to meet manufacturing demands, then productivity increases, but device performance consistency deteriorates
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the drive strength of output drivers based on measured process, voltage, and temperature conditions. The system modifies electrical parameters (transistor gate voltages) to compensate for PVT variations, ensuring consistent output signal characteristics across different manufacturing conditions and operating environments.
Solution Approach 2:
The patent implements feedback mechanisms by measuring actual output signal slew rates and using this information to adjust pre-driver and driver circuit parameters. The feedback loop compares measured performance against target specifications and automatically adjusts control voltages to maintain desired output characteristics, resolving the contradiction between manufacturing variability and performance consistency.
2Manufacturing precision
If control circuitry is added to compensate for PVT variations, then device performance consistency improves, but device complexity increases
Solution Approach 1:
The patent applies self-service by implementing automatic self-adjustment mechanisms where the output driver circuitry monitors its own performance and autonomously adjusts its parameters to maintain specified output characteristics. The system uses internal measurements of slew rate and automatically modifies pre-driver control voltages without requiring external calibration or complex control logic, thereby improving consistency while minimizing added complexity.
3Reliability
If iterative tuning and manufacturing adjustments are performed, then output signal integrity improves, but manufacturing cost and time increase
Solution Approach 1:
The patent applies preliminary action by pre-characterizing transistors during fabrication and storing their parameters in non-volatile memory. This preliminary measurement and storage of device characteristics eliminates the need for iterative tuning during assembly and operation. The system uses these pre-captured parameters to directly configure optimal drive strengths, ensuring signal integrity from the first operation without time-consuming iterative adjustments.
Data Source
AI summary
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.