DRAM and SOC Package-on-Package Substrate Segmentation
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Solution Overview
Problem
The dynamic random access memory (DRAM) industry faces challenges in achieving high-performance packaging due to the limitations of existing DDR DRAM technologies, such as LP-DDR2 and DDR3, which hinder the integration of DRAM and system-on-chip (SOC) in a single integrated circuit package, particularly due to signal integrity issues and physical space constraints.
Innovation Solution
The proposed solution involves various packaging configurations and architectures that allow for the stacking of DRAM and SOC in a single IC package using package-on-package (POP) technology, including modified ball arrangements and the use of interposers or windows in the package substrate to create additional space for the SOC, enabling reduced package size and compatibility with both 32-bit and 64-bit DDR configurations without requiring design changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM and SOC are integrated in a single IC package using POP technology, then signal integrity and high-speed performance are improved, but package size and design complexity increase
Solution Approach 1:
The package substrate is divided into multiple regions including a first region for DRAM package connection and a second region for SOC connection. This segmentation allows independent optimization of each region's layout and connection scheme, improving signal integrity while managing complexity through modular design
Solution Approach 2:
A package substrate acts as an intermediary between the DRAM package and SOC, providing a dedicated interface layer that manages signal routing, impedance control, and physical positioning. This intermediary structure enables high-speed signaling while isolating the complexity of integration from both the DRAM and SOC components
2Adaptability or versatility
If DRAM package pins are spread around the periphery to allow SOC placement, then integration is enabled, but signal trace length increases affecting performance
Solution Approach 1:
Different regions of the package substrate are assigned different functions: the first region optimizes for DRAM package connectivity while the second region optimizes for SOC connectivity. This local optimization allows short signal traces in the SOC region while maintaining periphery pin distribution for integration flexibility
Solution Approach 2:
The design transitions from a two-dimensional pin distribution problem to a three-dimensional package architecture by stacking the DRAM package above the SOC with vertical interconnections through the package substrate. This dimensional change reduces signal trace lengths while maintaining integration capability
3Productivity
If ultra-wide I/O DRAM with TSV technology is used to address bandwidth challenges, then bandwidth is improved, but manufacturing cost and redesign requirements increase
Solution Approach 1:
The design uses standard LP-DDR3 or DDR4 DRAM packages with conventional pin distributions instead of expensive ultra-wide I/O DRAM with TSV technology. The package substrate replicates the necessary I/O capacity through optimized routing and multi-lane configurations, achieving equivalent bandwidth at lower manufacturing cost
Solution Approach 2:
The design changes the package substrate's electrical parameters including trace impedance, signal voltage levels, and timing characteristics to optimize performance with standard DRAM packages. This parameter optimization enables high bandwidth utilization without requiring costly TSV technology or frequent redesigns for new DRAM generations
Data Source
Figure 1~3A
Figure 3B~3D
Figure 4A~4C
AI summary
An integrated circuit package includes a first memory die having a first set of connections, a second memory die arranged adjacent to the first memory die, the second memory die having a second set of connections, a first substrate having a first opening and a second opening, the first substrate having a third set of connections to connect to the first set of connections of the first memory die via the first opening and a fourth set of connections to connect to the second set of connections of the second memory die via the second opening, and a second substrate having a first integrated circuit disposed thereon. The first substrate is connected to the second substrate with the first integrated circuit disposed between the first substrate and second substrate.