DRAM Memory Spacer Air Gaps for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing technologies for fabricating Dynamic Random Access Memory (DRAM) devices face challenges in increasing density and improving performance, primarily due to limitations in scaling down DRAM size.
Innovation Solution
The method involves forming conductive wire structures and spacer structures over a semiconductor substrate, depositing conductive materials, patterning to form conductive strips, depositing a fill layer, cutting the conductive strips, and performing an etching process to remove the fill layer and form gaps in the spacer structures, resulting in a semiconductor memory structure with air gaps that reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the DRAM size is scaled down to increase density, then the device density improves, but the parasitic capacitance increases and performance deteriorates
Solution Approach 1:
The patent introduces air gaps (porous structures) within the spacer structures to reduce parasitic capacitance. The air gaps create void spaces that lower the dielectric constant in critical regions, thereby reducing capacitive coupling between adjacent conductive elements while maintaining the compact scaled-down geometry needed for high device density.
Solution Approach 2:
The spacer structures are formed as composite materials combining dielectric material and air gaps. This composite structure allows the spacer to provide both mechanical support and electrical isolation functions while reducing parasitic capacitance through the air gap portions, enabling continued scaling without performance degradation.
2Object-generated harmful factors
If the etching process is performed to remove fill layer and form gaps, then the air gaps are formed to reduce parasitic capacitance, but the negative effects of the etching process increase
Solution Approach 1:
The patent introduces a fill layer as an intermediary material that is selectively removed by the etching process. The fill layer serves as a sacrificial material that protects underlying structures during etching while enabling the formation of air gaps. This intermediary approach allows the etching process to be performed more safely with reduced negative effects on the final device structure.
Solution Approach 2:
The fill layer is deposited beforehand to define the regions where air gaps will ultimately form. This preliminary action prepares the structure for subsequent etching by providing a controlled material that can be selectively removed, thereby reducing the complexity and negative effects of the etching process while ensuring precise air gap formation.
3Ease of manufacture
If the spacer structures are formed with solid dielectric material, then the manufacturing process is simpler, but the parasitic capacitance is higher
Solution Approach 1:
The spacer structures are segmented into solid dielectric portions and air gap portions. This segmentation allows different regions of the spacer to serve different functions: the solid portions provide mechanical support and processability, while the air gap portions reduce parasitic capacitance. The segmented structure is achieved through selective removal of fill material, balancing manufacturing ease with electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of semiconductor memory devices by reducing parasitic capacitance through the formation of air gaps in the spacer structures, thereby improving manufacturing productivity and reducing the negative effects of the etching process.
Implementation Method 1
performing an etching process to remove the fill layer and form a plurality of gaps in the spacer structures
Implementation Method 2
depositing conductive materials between the conductive wire structures and over the conductive wire structures
Data Source
AI summary
A method for forming a semiconductor memory structure includes forming a plurality of conductive wire structures over a semiconductor substrate, and forming a plurality of spacer structures along the sidewalls of the conductive wire structures. Each of the spacer structures includes a first spacer. The method also includes forming a plurality of dielectric strips across the conductive wire structures, forming a plurality of conductive strips over the conductive wire structures and the dielectric strips, performing a patterning process on the conductive strips to form a plurality of conductive pads, and removing the first spacer of each of the spacer structures to form a gap in each of the spacer structures.