Two-Stage Hybrid Memory Buffer for Multi-Stream NVM Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory sub-systems with a single buffer, either external DRAM or internal SRAM, struggle to support a high number of streams at high performance, leading to increased costs, power consumption, and form factor issues when scaling to support multiple streams like 32 to 1024 streams.
Innovation Solution
A two-stage hybrid memory buffer is introduced, comprising a host buffer (DRAM) and a staging buffer (on-chip SRAM), where data from multiple streams is segregated and processed for error protection before being written to NVM memory, allowing for scalable support of multiple streams while maintaining performance and cost efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single buffer (external DRAM or internal SRAM) is used in conventional memory sub-systems, then the system structure is simple, but the system cannot support a high number of streams at high performance
Solution Approach 1:
The buffer is divided into two distinct stages: a first buffer (host buffer) that receives data from the host system and a second buffer (staging buffer) that prepares data for NVM programming. This segmentation allows each buffer to be optimized for its specific function, enabling support for multiple streams while maintaining manageable complexity through specialized design.
2Productivity
If internal SRAM is used to support multiple streams, then the bandwidth and performance are high, but the cost and die area become prohibitive
Solution Approach 1:
Different buffer regions are assigned different memory types based on their specific functional requirements. The first buffer uses external DRAM for cost-effective bulk storage, while the second buffer uses internal SRAM for high-speed staging operations. This local quality differentiation optimizes bandwidth where needed while controlling overall cost.
3Ease of manufacture
If external DRAM is used for buffering, then the cost is lower, but the bandwidth and performance are significantly reduced
Solution Approach 1:
The buffer system is segmented into two stages with different memory technologies. External DRAM provides the primary buffer at lower cost, while internal SRAM provides a high-bandwidth staging buffer. This segmentation allows the system to achieve high overall bandwidth through the SRAM stage without the prohibitive cost of making the entire buffer system high-performance.
4Adaptability or versatility
If the buffer size is increased to support more streams, then the number of streams supported increases, but the power consumption increases
Solution Approach 1:
The buffer system uses different memory types with different power characteristics in different locations. External DRAM consumes less power for bulk storage, while internal SRAM consumes more power but only for the smaller staging buffer that requires high-speed access. This local quality differentiation enables supporting multiple streams while controlling overall power consumption.
Data Source
AI summary
Described herein are embodiments related to a two-stage hybrid memory buffer for multiple streams in memory sub-systems. A processing device determines that first write data of a first stream stored in a host buffer component satisfies a threshold to program a first programming unit. The processing device transfers the first write data to the staging buffer component from the host buffer component, and writes the first write data from the staging buffer component as the first programming unit to a first die of multiple non-volatile memory (NVM) dies. The processing device determines that second write data of a second stream satisfies a threshold to program a second programming unit, transfers the second write data to the staging buffer component from the host buffer component, and writes the second write data from the staging buffer component as the second programming unit to a second die of the multiple NVM dies.