DRAM Stacking Beyond Logic Chip Edges for Capacity
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Solution Overview
Problem
The existing three-dimensional integrated circuit (3D IC) technology using vertical through-silicon vias (TSVs) is limited by the maximum memory capacity due to the size of the underlying logic chip, which restricts the number of stacked memory devices and results in a high overall cost for increased memory capacity.
Innovation Solution
The proposed solution involves a logic chip sandwiched between two supporting substrates with memory stacks arranged side by side, where at least a portion of the memory stacks extend past the logic chip's edges and are supported by these substrates, allowing for additional columns of stacked memory devices and enhanced thermal conductivity through the supporting substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the logic chip is increased to accommodate more stacked memory devices, then the memory capacity is improved, but the overall cost is increased accordingly
Solution Approach 1:
The patent extends memory stacks beyond the lateral boundaries of the logic chip onto the supporting substrate, utilizing the third dimension (vertical extension beyond chip edges) to increase memory capacity without increasing the logic chip area. This allows memory devices to be positioned in a spatial region that does not occupy additional logic chip real estate, thereby increasing capacity without proportionally increasing manufacturing cost.
2Quantity of substance
If the size of the logic chip is increased to accommodate more stacked memory devices, then the memory capacity is improved, but the die size for the logic chip is increased
Solution Approach 1:
The patent positions memory stacks such that they extend past the lateral edges of the logic chip and are supported by the supporting substrate. This dimensional extension allows the memory capacity to increase while the logic chip die size remains constant, as the additional memory devices are supported outside the logic chip boundaries.
3Area of stationary object
If conventional stacking approaches are used, then the substrate footprint is reduced, but the memory capacity is limited by the logic chip size
Solution Approach 1:
The patent utilizes the supporting substrate area outside the logic chip boundaries to accommodate additional memory stacks. By extending memory devices laterally beyond the logic chip edges and supporting them on the substrate, the system increases memory capacity without increasing the substrate footprint, as the memory stacks utilize the existing substrate area that would otherwise be empty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a 50% increase in memory capacity and interconnection bandwidth while maintaining a more affordable die size for the logic chip, along with improved thermal transmittance by utilizing the supporting substrates for heat dissipation.
Implementation Method 1
The area of the supporting substrate not covered by the stacked memory devices may provide a heat path to transfer heat generated by the logic chip to an overlying heat sink that is in contact with the tops of the memory devices. Therefore, the thermal transmittance of the IC system is enhanced.
Data Source
AI summary
Embodiments of the invention provide an integrated circuit system, which includes a first supporting substrate and a second supporting substrate, a logic chip disposed between the first supporting substrate and the second supporting substrate, and a plurality of memory stacks disposed adjacent to one another on a surface of the logic chip. The logic chip is separated from the first supporting substrate and the second supporting substrate by a distance such that at least a portion of a first memory stack in the plurality of memory stacks extending outwards past a first side edge of the logic chip is supported by the first supporting substrate, and at least a portion of a second memory stack in the plurality of memory stacks extending outwards past a second side edge of the logic chip that is opposite to the first side edge is supported by the second supporting substrate.