DRAM Storage Device Data Copying and ECC Correction
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Solution Overview
Problem
Conventional solid state drives experience decreased performance during writing and erasing operations due to inefficient data handling, leading to prolonged data transfer times and potential data loss during power interruptions.
Innovation Solution
A DRAM-based storage device with a control circuit and dynamic random access memory (DRAM) that includes a buffering area and a host accessing area, where data is automatically copied from the host accessing area to the buffering area at predetermined intervals, with error correction and encoding operations performed to ensure accurate data transfer and storage in non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored in DRAM buffer for temporary storage, then data access speed is improved, but data loss risk increases during power interruptions
Solution Approach 1:
The DRAM buffer is divided into two distinct regions: a volatile memory region for high-speed temporary storage and a non-volatile memory region for reliable data persistence. This segmentation allows the system to leverage the speed advantage of DRAM while mitigating the data loss risk through the non-volatile portion, resolving the contradiction between speed and reliability.
2Measurement precision
If ECC decoding operation is performed on copied data, then data accuracy is improved, but processing time increases
Solution Approach 1:
The system performs ECC decoding operations on data copies in advance before power interruption occurs. By preparing and verifying data accuracy beforehand, the system ensures data integrity without needing to perform time-consuming verification operations during critical power loss moments, thus reducing overall processing time while maintaining accuracy.
3Stability of the object's composition
If automatic data copying is performed at predetermined intervals, then data consistency is improved, but device complexity increases
Solution Approach 1:
The control circuit automatically initiates and manages data copying operations between the volatile and non-volatile memory regions at predetermined intervals without requiring external intervention. This self-service mechanism maintains data consistency through periodic synchronization while keeping the control logic contained within the existing DRAM controller, thereby avoiding significant increases in overall device complexity.
Data Source
AI summary
A DRAM-based storage device includes a DRAM and a control circuit. The DRAM includes a buffering area and a host accessing area. A data is stored in the host accessing area. The control circuit is electrically connected with the DRAM. The control circuit copies a portion of the data from the host accessing area to the buffering area at a predetermined time interval counted by the control circuit. Before the portion of the data is written to the buffering area, a first ECC decoding operation is performed on the portion of the data to correct error bits contained therein. If the portion of the data is corrected, the control circuit rewrites the corrected portion of the data into the host accessing area.