Strobe Signal Control Unit for DDR DRAM Collision Avoidance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with multiple DDR DRAM chips, collisions between data strobe signals can occur when chips with different address directions are connected in common, leading to increased circuit current and unstable operation, hindering high-speed performance.
Innovation Solution
A semiconductor device configuration where the data strobe signal of one chip alternates with that of another chip, with a strobe signal control unit determining the read state of connected chips to delay the output start timing of the data strobe signal, ensuring the latter half of the preamble period coincides with the postamble period of the other chip's signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple DDR DRAM chips are connected in parallel with common DQS terminals, then the device capacity is increased and mounting area is reduced, but data strobe signal collisions occur causing increased circuit current and unstable operation
Solution Approach 1:
The patent applies preliminary action by detecting the read state of other chips before outputting the DQS signal. The control circuit checks whether other chips connected in parallel are in a read state, and only outputs the DQS signal when it is safe to do so, preventing signal collisions before they occur.
Solution Approach 2:
The patent implements feedback by having the control circuit continuously monitor the read states of other chips and adjust the DQS signal output timing accordingly. This feedback mechanism ensures that the DQS signal is output only when other chips are not in a read state, preventing collisions and maintaining signal stability.
2Speed
If data strobe signals are output simultaneously from multiple chips, then high-speed data transfer is achieved, but signal collisions occur leading to increased circuit current
Solution Approach 1:
The control circuit performs preliminary detection of other chips' read states before enabling DQS signal output. This preliminary action ensures that high-speed data transfer can proceed without signal collisions, as the timing is coordinated to avoid simultaneous output from multiple chips.
Solution Approach 2:
The patent employs periodic action by coordinating the DQS signal output with the read operation timing of other chips. The signal is output in periodic cycles that are synchronized with the read states of other chips, ensuring high-speed transfer while avoiding collisions that would increase current consumption.
3Ease of operation
If DQS terminals of multiple chips are connected in common, then ease of operation is improved, but through current flows across power supply and ground
Solution Approach 1:
The control circuit uses feedback to detect when other chips are in a read state and prevents DQS signal output during those periods. This feedback mechanism eliminates through current flow by ensuring that the DQS signal is only output when other chips are not actively reading, maintaining the simple common connection while preventing harmful current flow.
Data Source
AI summary
High-speed operation is achieved without increase in a circuit current and unstable operation of data strobe signal level due to collision between data strobe signals. Each of RAMs 11a and 11b outputs a data signal DQ and a data strobe signal DQS indicative of an output timing of the data signal. RAM 11a includes a strobe signal control unit 15a that determines whether RAM 11b connected in parallel with the RAM 11a is in a read state or not, and delays an output start timing of data strobe signal DQS when the RAM 11b is in the read state. Strobe signal control unit 15a of the RAM 11a controls output start timing so that a latter half portion of a preamble period of the data strobe signal DQS to be output coincides with a postamble period of the data strobe signal DQS output by the RAM 11b.