Common Read Leveling for 4-bit Wide DRAM Strobe Signals
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Solution Overview
Problem
In memory controllers, achieving common read or write leveling for data strobe signals from multiple ×4 memory devices is complex due to different arrival times of clock, command, control, and address signals, requiring multiple leveling settings and additional logic, area, and power.
Innovation Solution
A mechanism is provided for deskewing two strobe signals (DQS0 and DQS1) serving one byte, where the first strobe signal is anchored, and the second is deskewed against it to determine a common read or write leveling setting, allowing a single set of settings for the memory controller, using read and write deskew training processes that align DQS1 with DQS0 and adjust DQS1 write deskew delay lines to achieve alignment with clock signals from different memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate leveling settings are used for each DQS signal from multiple ×4 memory devices, then data alignment accuracy is improved, but controller complexity increases
Solution Approach 1:
The patent merges the leveling settings for multiple DQS signals by using a single common leveling value for all DQS signals while applying device-specific delay adjustments. This combines what would otherwise be separate per-DQS settings into a unified approach, reducing controller complexity while maintaining alignment accuracy through the delay adjustment mechanism.
Solution Approach 2:
The patent segments the leveling adjustment into two parts: a common baseline leveling setting applied to all DQS signals, and device-specific delay adjustments applied to individual devices. This segmentation allows the controller to manage multiple devices with different arrival times using a simplified common setting plus targeted adjustments, rather than requiring completely separate settings for each signal.
2Measurement precision
If multiple leveling settings are maintained for different DQS signals, then data alignment is improved, but power consumption increases
Solution Approach 1:
The patent reduces power consumption by merging multiple leveling settings into a single common leveling setting that is shared across all DQS signals. This eliminates the need for the controller to maintain and update multiple separate settings, reducing the computational and memory resources required, thereby lowering power consumption while still achieving proper alignment through device-specific delay adjustments.
3Reliability
If device-specific delay adjustments are applied, then arrival time differences are compensated, but signal path complexity increases
Solution Approach 1:
The patent applies device-specific delay adjustments during the leveling training phase before normal operation begins. By pre-calculating and setting the appropriate delay values for each device based on their arrival time characteristics, the system compensates for timing differences in advance. During normal operation, these pre-set delays are simply applied without requiring complex real-time adjustments, thus achieving synchronization without ongoing signal path complexity.
Data Source
AI summary
System and method of read deskew training for ×4 mode memory control interface configurations. A read deskew training process includes aligning the two strobe signals serving one byte before deskewing the data bits against their corresponding strobe signals. A deskew setting of a variable delay line associated with the second strobe signal is adjusted to align the second strobe signal with reference to the first strobe signal. By aligning the two strobe signals with respect to each other, the read leveling settings can be common within the byte even the two DQS signals are transmitted to or received from two different memory storage devices.