DRAM Sub-Page ECC Write Circuit for Faster Read-Modify-Write
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Solution Overview
Problem
The increasing bit errors in dynamic random access memories (DRAMs) due to scaled-down manufacturing processes necessitate improved integrity and efficiency in semiconductor memory devices, particularly in system-level performance, power consumption, and internal read-modify-write operations.
Innovation Solution
A semiconductor memory device incorporating a memory cell array, an error correction circuit, an input/output gating circuit, and a control logic circuit that performs error-correcting code (ECC) decoding, generates parity data, and executes internal read-modify-write operations in response to a single command, enhancing system performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the manufacturing process is scaled down to increase yield, then productivity is improved, but bit errors in memory cells increase
Solution Approach 1:
The patent divides the memory page into multiple sub-pages and implements separate error correction circuits for each sub-page. This segmentation allows error correction to be performed on smaller data units independently, improving the effectiveness of error correction in scaled-down memory cells while maintaining high manufacturing yield.
Solution Approach 2:
The patent changes the parameter of error correction granularity by introducing sub-page level error correction instead of page-level correction. It also implements dynamic parity data generation based on write operations, changing the temporal parameter of when error correction is applied (during write operations rather than only during read operations).
2Reliability
If traditional separate read-modify-write operations are performed, then data integrity can be maintained, but system-level performance decreases and power consumption increases
Solution Approach 1:
The patent merges the read operation, error correction operation, and write operation into a single integrated process. The error correction circuit corrects errors in the read data and generates corrected data that is immediately written back to memory in the same operation cycle, eliminating the need for separate read-modify-write operations and thereby improving system performance while maintaining data integrity.
Solution Approach 2:
The patent performs error correction as a preliminary action during the write operation itself. By correcting errors in the read data before the write operation completes and generating corrected parity data in advance, the system ensures data integrity is maintained while reducing the total number of operation cycles needed.
3Measurement precision
If multiple operation cycles are used for read-modify-write, then data accuracy can be ensured, but the time required for operations increases
Solution Approach 1:
The patent combines multiple operation cycles (read, error correction, write) into a single integrated operation cycle. The error correction circuit processes read data and generates corrected output that is immediately available for writing, eliminating the time delay associated with sequential operations while maintaining data accuracy through comprehensive error correction.
Solution Approach 2:
The patent maintains continuous useful action by piping the output of the error correction circuit directly to the write operation without intermediate delays. The corrected data flows continuously from the error correction stage to the write stage, ensuring that no time is lost between error correction and data writing, thereby reducing total operation time while preserving data accuracy.
Data Source
AI summary
Semiconductor memory device may include a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The control logic circuit may, in a first write operation mode, control the I/O gating circuit to select a sub-page, read a first unit of data including a first sub unit of data, a second sub unit of data and a first parity data from the sub-page, and provide the first unit of data to the error correction circuit. The control logic circuit may also control the error correction circuit to perform an error-correcting code decoding on the first unit of data to generate syndrome data, generate second parity data based on a portion of the first unit of data and generate third parity data based on a write parity data, the second parity data and the syndrome data.